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公开(公告)号：US20250072298A1
公开(公告)日：2025-02-27
申请号：US18655948
申请日：2024-05-06
Applicant: Jiangsu Jichuang Atomic Cluster Technology Research Institute Co., Ltd. , Nanjing University
Inventor： Fengqi SONG , Minhao ZHANG , Suyuan XIE , Wei JI , Yuanzhi TAN , Jun CHEN , Kangkang ZHANG , Bowen LIU , Luwei GU
Abstract: An atomic-scale cluster storage and compute device is successively provided with a substrate and oxide layer, a gate electrode, and a gate dielectric layer from bottom to top; at least one conductive electrode is provided on the gate dielectric layer, and one nanoscale gap is provided on each conductive electrode; two sides of the nanoscale gap are a source electrode and a drain electrode, and a combined molecular system is provided in the nanoscale gap; the combined molecular system is a composite system of one or more functional atoms and a single molecule, which forms good contact with a source electrode and a drain electrode, and the combined molecular system has the feature of a single electric dipole and bistable state. A combined molecular system of a single molecule with several functional atoms is constructed; the combined molecular system has the feature of a single electric dipole and bistable state.
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公开(公告)号：US12239027B2
公开(公告)日：2025-02-25
申请号：US18117918
申请日：2023-03-06
Applicant: Google LLC
Inventor： Brian James Burkett , Ofer Naaman , Anthony Edward Megrant , Theodore Charles White
Abstract: Methods, systems and apparatus for forming Josephson junctions with reduced stray inductance. In one aspect, a device includes a substrate; a first superconductor layer on the substrate; an insulator layer on the first superconductor layer; a second superconductor layer on the insulator layer, wherein the first superconductor layer, the insulator layer, and the second superconductor layer form a superconductor tunnel junction; and a third superconductor layer directly on a surface of the first superconductor layer and directly on a surface of the second superconductor layer to provide a first contact to the superconducting tunnel junction and a second contact to the superconductor tunnel junction, respectively.
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公开(公告)号：US20250044699A1
公开(公告)日：2025-02-06
申请号：US18784732
申请日：2024-07-25
Applicant: Riken
Inventor： Harumi Hayakawa , Koichi Kusuyama
Abstract: A film deposition method including installing a substrate on a turntable of a spin coating device such that a first main surface faces the turntable, and adding a first liquid having viscosity dropwise onto a second main surface of the substrate; holding the substrate in the same state until the first liquid added dropwise reaches the first main surface side from the second main surface side through a through-hole; otating the substrate together with the turntable; and heating the first liquid together with the substrate.
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公开(公告)号：US20250040448A1
公开(公告)日：2025-01-30
申请号：US18442149
申请日：2024-02-15
Applicant: Ambature, Inc.
Inventor： Archana Tiwari , Mitchell Robson , Priyanka Brojabasi
Abstract: In some implementations of the invention, a silicon dioxide (SiO2) insulating layer added between islands of a top YBCO layer of a Josephson Junction isolates a contact layer from YBCO (or other conductive components) in the Josephson Junction. In some implementations of the invention, a SiO2 insulating layer added between islands of a bottom YBCO layer of adjacent Josephson Junctions isolates the contact layer or other components from YBCO (or other conductive components) in the Josephson Junction. In some implementations of the invention, an etch stop layer may be deposited over the islands of the top YBCO layer prior to adding the SiO2 insulating layer. This etch stop layer protects the top YBCO layer during the adding of the SiO2 insulating layer and during subsequent formation of a via through the SiO2 to the etch stop layer.
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公开(公告)号：US12207568B2
公开(公告)日：2025-01-21
申请号：US18315401
申请日：2023-05-10
Inventor： Liangliang Ma , Bing You , Nianci Wang , Jie Zheng , Wenshu Liu
Abstract: Disclosed are a fabrication method for a superconducting circuit and a superconducting quantum chip. The fabrication method includes: determining, on a substrate, a first junction region located between a first electrical element and a second electrical element, and a second junction region located between a first conductive plate and a second conductive plate that are formed in advance; forming a Josephson junction in the second junction region; detect an electrical parameter of the Josephson junction, and determining whether the electrical parameter is within a target parameter range; if yes, separating the Josephson junction through cutting, and moving the Josephson junction to the first junction region; and forming a first connection structure connecting the first superconducting layer to the first electrical element and a second connection structure connecting the second superconducting layer to the second electrical element.
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Patent Agency Ranking
公开(公告)号：US12205734B2
公开(公告)日：2025-01-21
申请号：US18032806
申请日：2021-09-02
Applicant: SHANGHAI JIAO TONG UNIVERSITY
Inventor： Jie Sheng , Xueliang Wang , Zhuyong Li , Longbiao Wang
Abstract: A variable-structure stacked cable topology includes: a plurality of sections of stacked cables. The plurality of sections of the stacked cables are connected sequentially. The sections of the stacked cables includes a plurality of base tapes at an equal quantity. The plurality of base tapes are connected mutually. At least one of the plurality of base tapes is a superconducting tape. A cable topological structure is formed by sequentially connecting a plurality of sections of stacked cables. Each of the sections of the stacked cables is provided with superconducting tapes or a combination of superconducting tapes and copper tapes to form a variable-structure cable topological structure. By packaging a different number of superconducting tapes in each area, this section of cable can be twisted into a coil in such a way that a critical current of the whole coil can be approximately uniform along a length direction of the cable.
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公开(公告)号：US12193338B2
公开(公告)日：2025-01-07
申请号：US17094694
申请日：2020-11-10
Applicant: RAYTHEON BBN TECHNOLOGIES CORP.
Inventor： Graham Earle Rowlands , Thomas Akira Ohki , Guilhem Jean Antoine Ribeill , Minh-Hai Nguyen
Abstract: A reservoir computer. In some embodiments, the reservoir computer includes a series array of Josephson junctions, a coupling impedance, and a readout circuit. In some embodiments, the series array of Josephson junctions includes a plurality of Josephson junctions, connected in series; the coupling impedance is connected in parallel with the series array of Josephson junctions; and the readout circuit is connected to at least three nodes of the series array of Josephson junctions.
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公开(公告)号：US20250006819A1
公开(公告)日：2025-01-02
申请号：US18829478
申请日：2024-09-10
Inventor： Robert A. Makin, III , Steven Michael Durbin
Abstract: A method of fabricating a superconducting device includes determining a target transition temperature and utilizing a predefined quantitative relationship between superconducting transition temperature and an order parameter for at least one superconducting material composition is utilized to select a superconductor material composition that is capable of providing a target transition temperature. Process parameters may be controlled to form a superconductor device comprising at least one superconductor material having a material composition providing the target transition temperature.
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公开(公告)号：US12178142B2
公开(公告)日：2024-12-24
申请号：US17097252
申请日：2020-11-13
Applicant: International Business Machines Corporation
Inventor： Stephen M. Gates , Russell A. Budd , Kevin Shawn Petrarca , Vivekananda P. Adiga , Douglas Max Gill
Abstract: The subject disclosure is directed towards layered substrate structures with aligned optical access to electrical devices formed thereon for laser processing and electrical device tuning. According to an embodiment, a layered substrate structure is provided that comprises an optical substrate having a first surface and a second surface and a patterned bonding layer formed on the second surface that comprises a bonding region and an open region, wherein the open region exposes a portion of the second surface. The layered substrate structure further comprises a device chip bonded to the patterned bonding layer via the bonding region and comprising at least one electrical component aligned with the optical substrate and the open region. The at least one electrical component can include for example, a thin film wire, an air bridge, a qubit, an electrode, a capacitor or a resonator.
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公开(公告)号：US20240423099A1
公开(公告)日：2024-12-19
申请号：US18823322
申请日：2024-09-03
Applicant: Fujitsu Limited
Inventor： Tsuyoshi TAKAHASHI
Abstract: A method for manufacturing a Josephson junction device, includes: forming a mask layer on a substrate; forming, with the mask layer as a mask, a first superconducting film above the substrate by first film formation from a first oblique direction; forming an insulating film at a surface of the first superconducting film; and forming, with the mask layer as the mask, a second superconducting film having a region overlapping the first superconducting film via the insulating film by second film formation from a second oblique direction, wherein the mask layer includes: a first mask pattern in a first region of the substrate and a second mask pattern that is positioned in a second region of the substrate, and the second region is positioned closer to an end of the substrate than the first region.
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