公开(公告)号：US11944022B2

公开(公告)日：2024-03-26

申请号：US17446328

申请日：2021-08-30

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Laurent Grenouillet ,  Marios Barlas ,  Etienne Nowak

IPC: H10N70/00 ,  G11C13/00 ,  H10B63/00

CPC classification number: H10N70/883 ,  G11C13/0002 ,  H10B63/00 ,  H10N70/841

Abstract: A resistive memory cell may be provided with a first electrode and a second electrode arranged on either side of a dielectric layer and facing an interface between a first region and a second region, The first and second region may have different compositions in terms of doping and/or dielectric constant, so as to confine the zone of reversible creation of a conductive filament at the interface.

公开(公告)号：US10985317B2

公开(公告)日：2021-04-20

申请号：US16331729

申请日：2017-09-08

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Marios Barlas ,  Philippe Blaise ,  Laurent Grenouillet ,  Benoît Sklenard ,  Elisa Vianello

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: A device for selecting a storage cell, includes a first electrode, a second electrode and an oxide layer disposed between the first electrode and the second electrode, wherein the oxide layer is doped with a first element from column IV of the periodic table.

公开(公告)号：US11189792B2

公开(公告)日：2021-11-30

申请号：US16331714

申请日：2017-09-08

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Laurent Grenouillet ,  Marios Barlas ,  Philippe Blaise ,  Benoît Sklenard ,  Elisa Vianello

IPC: H01L45/00 ,  H01L27/24

Abstract: A resistive non-volatile memory cell includes a first electrode, a second electrode and an oxide layer disposed between the first electrode and the second electrode, the memory cell being capable of reversibly switching between: —a high resistance state obtained by applying a first bias voltage between the first electrode and the second electrode; and—a low resistance state obtained by applying a second bias voltage between the first electrode and the second electrode; the oxide layer including a switching zone forming a conduction path prioritised for the current passing through the memory cell when the memory cell is in the low resistance state. The oxide layer includes a first zone doped with aluminium or silicon, the aluminium or silicon being present in the first zone with an atomic concentration that is selected so as to locate the switching zone outside the first zone.

公开(公告)号：US10446564B2

公开(公告)日：2019-10-15

申请号：US15977357

申请日：2018-05-11

Applicant: Commissariat a l'energie atomique et aux energies alternatives ,  Universite d'Aix-Marseille

Inventor： Jean-Michel Portal ,  Marios Barlas ,  Laurent Grenouillet ,  Elisa Vianello

IPC: H01L27/115 ,  H01L27/11524 ,  H01L45/00 ,  H01L27/24

Abstract: The invention relates to a non-volatile memory that comprises selection transistors. Each selection transistor includes a layer of semiconductor material with a channel region and conduction electrodes, a gate stack including a gate electrode and a gate insulator, an isolation trench between the transistors, a storage structure of the RRAM type comprising a control electrode, and a dielectric layer formed under the control electrode and in the same material as the gate insulator, comprising a central part directly above the isolation trench and ends extending directly above conduction electrodes, and configured so as to form conducting filaments. The said storage structure and the said selection transistors are formed in the same pre-metallization layer.

公开(公告)号：US20180331115A1

公开(公告)日：2018-11-15

申请号：US15977357

申请日：2018-05-11

Applicant: Commissariat a l'energie atomique et aux energies alternatives ,  Universite d'Aix-Marseille

Inventor： Jean-Michel Portal ,  Marios Barlas ,  Laurent Grenouillet ,  Elisa Vianello

IPC: H01L27/11524 ,  H01L27/24 ,  H01L45/00

Abstract: The invention relates to a non-volatile memory that comprises selection transistors. Each selection transistor includes a layer of semiconductor material with a channel region and conduction electrodes, a gate stack including a gate electrode and a gate insulator, an isolation trench between the transistors, a storage structure of the RRAM type comprising a control electrode, and a dielectric layer formed under the control electrode and in the same material as the gate insulator, comprising a central part directly above the isolation trench and ends extending directly above conduction electrodes, and configured so as to form conducting filaments. The said storage structure and the said selection transistors are formed in the same pre-metallization layer.