公开(公告)号：US12133477B2

公开(公告)日：2024-10-29

申请号：US17873594

申请日：2022-07-26

Applicant: HEFEI RELIANCE MEMORY LIMITED

Inventor： Zezhi Chen ,  Zhichao Lu ,  Liang Zhao

IPC: G11C13/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10N70/245 ,  G11C13/0007 ,  G11C13/0011 ,  H10N70/826 ,  H10N70/883

Abstract: A resistive random access memory (RRAM) and a method for operating the RRAM are disclosed. The RRAM includes at least two successively stacked conductive layers and a resistive switching layer situated between every adjacent two conductive layers, wherein a migration interface with an interface effect is formed at each interface between one conductive layer and the resistive switching layer in contact therewith, wherein the migration interface regulates, by the interface effect, vacancies formed in the resistive switching layer under the effect of an electrical signal. The regulation includes at least one of absorption, migration and diffusion.

公开(公告)号：US20240215468A1

公开(公告)日：2024-06-27

申请号：US18347418

申请日：2023-07-05

Applicant: SK hynix Inc.

Inventor： Kyung Seop KIM ,  Chi Ho Kim ,  Young Cheol Song ,  Jae Wan Choi

IPC: H10N70/00 ,  H10B63/00

CPC classification number: H10N70/883 ,  H10B63/84 ,  H10N70/023 ,  H10N70/063 ,  H10N70/826 ,  H10N70/841

Abstract: A semiconductor device is provided. The semiconductor device according to an implementation of the disclosed technology may include a variable resistance layer; a selector layer disposed over or under the variable resistance layer; a first protective layer disposed on sidewalls of the variable resistance layer and sidewalls of the selector layer, the first protective layer including silicon (Si) and nitrogen (N) and having a nitrogen (N) content higher than a silicon (Si) content; and a second protective layer disposed over the first protective layer, the second protective layer including silicon (Si) and nitrogen (N) and having a silicon (Si) content higher than a nitrogen (N) content.

公开(公告)号：US11972796B2

公开(公告)日：2024-04-30

申请号：US17960660

申请日：2022-10-05

Applicant: Kioxia Corporation

Inventor： Kikuko Sugimae ,  Yusuke Arayashiki

IPC: G11C13/00 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  H10B63/84 ,  H10N70/063 ,  H10N70/245 ,  H10N70/8416 ,  H10N70/883 ,  G11C2013/0045 ,  G11C2013/0078 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/33 ,  G11C2213/34 ,  G11C2213/71 ,  H10N70/826 ,  H10N70/8833 ,  H10N70/8836

Abstract: A memory device according to an embodiment includes a first interconnect, a second interconnect, a first variable resistance member, a third interconnect, a second variable resistance member, a fourth interconnect, a fifth interconnect and a third variable resistance member. The first interconnect, the third interconnect and the fourth interconnect extend in a first direction. The second interconnect and the fifth interconnect extend in a second direction crossing the first direction. The first variable resistance member is connected between the first interconnect and the second interconnect. The second variable resistance member is connected between the second interconnect and the third interconnect. The third variable resistance member is connected between the fourth interconnect and the fifth interconnect. The fourth interconnect is insulated from the third interconnect.

公开(公告)号：US11944022B2

公开(公告)日：2024-03-26

申请号：US17446328

申请日：2021-08-30

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Laurent Grenouillet ,  Marios Barlas ,  Etienne Nowak

IPC: H10N70/00 ,  G11C13/00 ,  H10B63/00

CPC classification number: H10N70/883 ,  G11C13/0002 ,  H10B63/00 ,  H10N70/841

Abstract: A resistive memory cell may be provided with a first electrode and a second electrode arranged on either side of a dielectric layer and facing an interface between a first region and a second region, The first and second region may have different compositions in terms of doping and/or dielectric constant, so as to confine the zone of reversible creation of a conductive filament at the interface.

公开(公告)号：US11937521B2

公开(公告)日：2024-03-19

申请号：US17374022

申请日：2021-07-13

Applicant: International Business Machines Corporation

Inventor： Chanro Park ,  Kangguo Cheng ,  Ruilong Xie ,  Choonghyun Lee

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/068 ,  H10N70/023 ,  H10N70/046 ,  H10N70/063 ,  H10N70/066 ,  H10N70/245 ,  H10N70/826 ,  H10N70/8416 ,  H10N70/883 ,  H10B63/30

Abstract: A non-volatile memory device and a semiconductor structure including a vertical resistive memory cell and a fabrication method therefor. The semiconductor structure including a target metal contact; a horizontal dielectric layer; and at least one vertically oriented memory cell, each vertically oriented memory cell including a vertical memory resistive element having top and bottom electrical contacts, and including a vertically-oriented seam including conductive material and extending vertically from, and electrically connected to, the bottom electrical contact, the vertically-oriented seam and the bottom electrical contact entirely located in the horizontal dielectric layer; and one of the top and bottom electrical contacts being electrically connected to the target metal contact. The target electrical contact can be electrically connected to a memory cell selector device.

公开(公告)号：US20240008292A1

公开(公告)日：2024-01-04

申请号：US18299811

申请日：2023-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keon Jae Lee ,  Sang Hyun Sung ,  Young Hoon Jung

IPC: H10B63/00 ,  H10B63/10 ,  H10N70/20 ,  H10N70/00 ,  G06N3/063

CPC classification number: H10B63/82 ,  H10B63/10 ,  H10N70/231 ,  H10N70/24 ,  H10N70/841 ,  H10N70/8828 ,  H10N70/883 ,  H10N70/026 ,  G06N3/063

Abstract: Disclosed is a neuromorphic memory element, which includes a first electrode; a second electrode; a first thin film layer adjacent to the first electrode between the first electrode and the second electrode and that is configured to emulate a neuronal plasticity by performing a volatile storage function based on a voltage difference between the first electrode and the second electrode; and a second thin film layer between the first thin film layer and the second electrode and that is configured to emulate a synaptic plasticity by performing a non-volatile storage function.

公开(公告)号：US11812676B2

公开(公告)日：2023-11-07

申请号：US16828242

申请日：2020-03-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Timothy Mathew Philip ,  Lawrence A. Clevenger ,  Kevin W. Brew

IPC: H10N70/20 ,  H10N70/00

CPC classification number: H10N70/861 ,  H10N70/011 ,  H10N70/231 ,  H10N70/253 ,  H10N70/823 ,  H10N70/826 ,  H10N70/8413 ,  H10N70/883 ,  H10N70/8828

Abstract: A phase change memory device is provided. The phase change memory device includes a phase change memory material within an electrically insulating wall, a first heater terminal in the electrically insulating wall, and two read terminals in the electrically insulating wall.

公开(公告)号：US11763889B2

公开(公告)日：2023-09-19

申请号：US17706087

申请日：2022-03-28

Applicant: Micron Technology, Inc.

Inventor： Benben Li ,  Akira Goda ,  Ramey M. Abdelrahaman ,  Ian C. Laboriante ,  Krishna K. Parat

IPC: G11C16/04 ,  G11C11/408 ,  G11C8/08 ,  H10B41/27 ,  H10B41/35 ,  H10B41/60 ,  H10B43/27 ,  H10B43/35 ,  H10B51/20 ,  H10B63/00 ,  H10N70/00

CPC classification number: G11C16/0475 ,  G11C8/08 ,  G11C11/4087 ,  H10B41/27 ,  H10B41/35 ,  H10B41/60 ,  H10B43/27 ,  H10B43/35 ,  H10B51/20 ,  H10B63/84 ,  H10N70/883 ,  G11C16/0483

Abstract: Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.

公开(公告)号：US11723292B2

公开(公告)日：2023-08-08

申请号：US16910609

申请日：2020-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yang Chang ,  Wen-Ting Chu ,  Kuo-Chi Tu ,  Yu-Wen Liao ,  Hsia-Wei Chen ,  Chin-Chieh Yang ,  Sheng-Hung Shih ,  Wen-Chun You

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/8265 ,  H10B63/30 ,  H10N70/011 ,  H10N70/063 ,  H10N70/066 ,  H10N70/20 ,  H10N70/24 ,  H10N70/826 ,  H10N70/841 ,  H10N70/8833 ,  H10N70/021 ,  H10N70/023 ,  H10N70/026 ,  H10N70/028 ,  H10N70/041 ,  H10N70/043 ,  H10N70/046 ,  H10N70/061 ,  H10N70/068 ,  H10N70/231 ,  H10N70/235 ,  H10N70/245 ,  H10N70/25 ,  H10N70/253 ,  H10N70/257 ,  H10N70/801 ,  H10N70/821 ,  H10N70/823 ,  H10N70/828 ,  H10N70/8413 ,  H10N70/8416 ,  H10N70/8418 ,  H10N70/8613 ,  H10N70/8616 ,  H10N70/881 ,  H10N70/882 ,  H10N70/883 ,  H10N70/884 ,  H10N70/8822 ,  H10N70/8825 ,  H10N70/8828 ,  H10N70/8836 ,  H10N70/8845

Abstract: The present disclosure, in some embodiments, relates to a memory device. The memory device includes a dielectric protection layer having sidewalls defining an opening over a conductive interconnect within an inter-level dielectric (ILD) layer. A bottom electrode structure extends from within the opening to directly over the dielectric protection layer. A variable resistance layer is over the bottom electrode structure and a top electrode is over the variable resistance layer. A top electrode via is disposed on the top electrode and directly over the dielectric protection layer.

公开(公告)号：US12108611B2

公开(公告)日：2024-10-01

申请号：US16941170

申请日：2020-07-28

Applicant: SK hynix Inc.

Inventor： Jae Hyun Han ,  Se Ho Lee ,  Hyangkeun Yoo

IPC: H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/30 ,  H10B63/82 ,  H10B63/84 ,  H10N70/24 ,  H10N70/245 ,  H10N70/253 ,  H10N70/823 ,  H10N70/841 ,  H10N70/8822 ,  H10N70/8828 ,  H10N70/883 ,  H10N70/8833 ,  H10N70/8836

Abstract: A nonvolatile memory device according to an embodiment includes a substrate, a resistance change layer disposed on the substrate, a gate electrode layers disposed on the resistance change layer, and a first electrode pattern layer and a second electrode pattern layer that are disposed in the substrate and contact different portions of the resistance change layer. The resistance change layer includes movable oxygen vacancies or movable metal ions.