公开(公告)号：US11176018B1

公开(公告)日：2021-11-16

申请号：US16219836

申请日：2018-12-13

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Aruna Aluri ,  Linwei Ding ,  Mitchell G. Poplack

IPC: G06F11/00 ,  G06F11/34 ,  G06F11/36 ,  G06F11/07 ,  G06F30/331

Abstract: A trace subsystem of an emulation system may generate differential frame data based upon successive frames. If one compression mode, the trace subsystem may set a flag bit and store differential frame data if there is at least one non-zero bit in the differential frame data. If the differential frame data includes only zero bits, the trace subsystem may set the flag bit without storing the frame data. In another compression mode, the computer may further compress the differential data if the frame data includes one (one-hot) or two (two-hot) non-zero bits. The controller may set flag bits to indicate one of all-zeroes, one-hot, two-hot, and random data conditions (more than two non-zero bits). For one-hot or two-hot conditions, the controller may store bits indicating the positions of the non-zero bits. For random data conditions, the controller may store the entire differential frame.

公开(公告)号：US11573883B1

公开(公告)日：2023-02-07

申请号：US16219860

申请日：2018-12-13

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Mitchell G. Poplack ,  Aruna Aluri ,  Linwei Ding

IPC: G06F11/34 ,  G06F30/20 ,  G01R31/3183 ,  H03M7/30

Abstract: A trace subsystem of an emulation system may generate differential frame data based upon successive frames. If one compression mode, the trace subsystem may set a flag bit and store differential frame data if there is at least one non-zero bit in the differential frame data. If the differential frame data includes only zero bits, the trace subsystem may set the flag bit without storing the frame data. In another compression mode, the computer may further compress the differential data if the frame data includes one (one-hot) or two (two-hot) non-zero bits. The controller may set flag bits to indicate one of all-zeroes, one-hot, two-hot, and random data conditions (more than two non-zero bits). For one-hot or two-hot conditions, the controller may store bits indicating the positions of the non-zero bits. For random data conditions, the controller may store the entire differential frame.

公开(公告)号：US11520531B1

公开(公告)日：2022-12-06

申请号：US17139163

申请日：2020-12-31

Applicant: Cadence Design Systems, Inc.

Inventor： Mitchell G. Poplack ,  Justin Schmelzer ,  Aruna Aluri

IPC: G06F3/06 ,  G06F11/34

Abstract: A system may include a synchronization device and an emulation chip including a processor and a memory. The processor may evaluate, during a first cycle, at least one of a set of one or more execution instructions in the memory or evaluation primitives configured to emulate a circuit, and evaluate, during a second cycle, at least one of the set of one or more execution instructions or a set of configured logic primitives. The synchronization device may interpose a gap period interposed between the first cycle and the second cycle such that during the gap period, the processor does not evaluate one or more instructions from the set of one or more execution instructions or re-evaluate primitives. The synchronization device may cause, during the first gap period, the emulation chip to perform refreshes on the memory of the emulation chip.