公开(公告)号：US11474844B1

公开(公告)日：2022-10-18

申请号：US17247927

申请日：2020-12-30

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Mitchell G. Poplack ,  Justin Schmelzer

IPC: G06F9/445 ,  G06F9/455

Abstract: Embodiments described herein include an emulator system having a synchronization subsystem comprising devices, organized in logical hierarchy, controlling synchronization of a system clock and system components during emulation execution. The devices of the logical hierarchy communicate bi-directionally, communicating status indicators upwards and execution instructions downwards. A TCI is designated “master TCI” and others are designated “slave TCIs.” The master TCI asserts a RDY status that propagates upwards to a root node for a number cycles. The slave TCIs execute in “infinite run” and continually assert the RDY status upwards to the root device regardless of the cycle count. The root node detects each RDY status and propagates downwards a GO instruction to the master TCI and the slave TCIs. In this way, the TCIs execute until the master TCI de-asserts RDY status. The result is only the master TCI is manipulated to, for example, start/stop emulation or perform iterative execution.

公开(公告)号：US10997343B1

公开(公告)日：2021-05-04

申请号：US16721543

申请日：2019-12-19

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Mitchell Poplack ,  Xiaolei Guo ,  Phung Truong ,  Justin Schmelzer

IPC: G06F17/50 ,  G01R31/00 ,  G06F11/00 ,  G06F30/343 ,  G01R31/3177 ,  G06F30/331 ,  G06F11/26 ,  G06F9/455 ,  G01R31/3185

Abstract: An emulation system may include an emulator. The emulator may include at least one chip and at least one FPGA. The chip may be associated with the FPGA. The FPGA may operate as a coprocessor to implement in-system scan test of the chip. In a scan mode of the in-system scan test, the coprocessor may transmit one or more in-system test instructions to the chip through its existing connections with the chip. The coprocessor may capture test response data from the chip in response to the one or more in-system test instructions through its existing connections with the chip. In an offline mode, the coprocessor may compare the test response data with expected response data to determine if the chips are functioning correctly.

公开(公告)号：US11520531B1

公开(公告)日：2022-12-06

申请号：US17139163

申请日：2020-12-31

Applicant: Cadence Design Systems, Inc.

Inventor： Mitchell G. Poplack ,  Justin Schmelzer ,  Aruna Aluri

IPC: G06F3/06 ,  G06F11/34

Abstract: A system may include a synchronization device and an emulation chip including a processor and a memory. The processor may evaluate, during a first cycle, at least one of a set of one or more execution instructions in the memory or evaluation primitives configured to emulate a circuit, and evaluate, during a second cycle, at least one of the set of one or more execution instructions or a set of configured logic primitives. The synchronization device may interpose a gap period interposed between the first cycle and the second cycle such that during the gap period, the processor does not evaluate one or more instructions from the set of one or more execution instructions or re-evaluate primitives. The synchronization device may cause, during the first gap period, the emulation chip to perform refreshes on the memory of the emulation chip.

公开(公告)号：US11156660B1

公开(公告)日：2021-10-26

申请号：US16721448

申请日：2019-12-19

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Mitchell Poplack ,  Xiaolei Guo ,  Phung Truong ,  Justin Schmelzer

IPC: G01R31/00 ,  G01R31/3177

Abstract: A system for testing of one or more electronic devices is disclosed. In an embodiment, a processor transmits one or more test vectors to the one or more electronic devices. The one or more test vectors are based upon configuration parameters of the processor and input-output parameters of the one or more electronic devices. The processor receives scan vectors from the one or more electronic devices in response to the plurality of test vectors. The processor verifies in-system behavior of the one or more electronic devices based upon comparing received scan vectors with expected scan vectors.