公开(公告)号：US20230350806A1

公开(公告)日：2023-11-02

申请号：US17661394

申请日：2022-04-29

Applicant: Cadence Design Systems, Inc.

Inventor： Avishai Tvila

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/602

Abstract: A prefetch circuit coupled to a cache memory circuit includes a storage circuit that stores multiple virtual-to-physical address map entries. In response to receiving an indication of a miss for an access request to the cache memory circuit, the prefetch circuit generates a prefetch address and compares it to a demand address included in the access request. In response to determining that the demand address and the prefetch address are in different memory pages, the prefetch circuit generates a prefetch request using physical page information retrieved from the storage circuit.

公开(公告)号：US12111765B2

公开(公告)日：2024-10-08

申请号：US17661394

申请日：2022-04-29

Applicant: Cadence Design Systems, Inc.

Inventor： Avishai Tvila

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/602

Abstract: A prefetch circuit coupled to a cache memory circuit includes a storage circuit that stores multiple virtual-to-physical address map entries. In response to receiving an indication of a miss for an access request to the cache memory circuit, the prefetch circuit generates a prefetch address and compares it to a demand address included in the access request. In response to determining that the demand address and the prefetch address are in different memory pages, the prefetch circuit generates a prefetch request using physical page information retrieved from the storage circuit.