公开(公告)号：US11023357B1

公开(公告)日：2021-06-01

申请号：US16583853

申请日：2019-09-26

Applicant: Cadence Design Systems, Inc.

Inventor： Ayman Hanna ,  Karam Abdelkader ,  Doron Bustan ,  Habeeb Farah ,  Thiago Radicchi Roque ,  Felipe Althoff

IPC: G06F11/36 ,  G06N20/00 ,  G06F30/30 ,  G06F30/33 ,  G06F30/333

Abstract: A method for sequential equivalence checking (SEC) of two representations of an electronic design may include using a processor, automatically selecting a plurality of cutpoints in the two representations of the electronic design; using a processor, automatically executing a prove-from strategy on the plurality of cut point pairs to identify a failed cut point pair in the two electronic designs; and using the processor, automatically extending a trace corresponding to the identified failed cut point pair to identify a deeper failed cut point pair or a failed output pair in the two electronic designs.