公开(公告)号：US11023357B1

公开(公告)日：2021-06-01

申请号：US16583853

申请日：2019-09-26

Applicant: Cadence Design Systems, Inc.

Inventor： Ayman Hanna ,  Karam Abdelkader ,  Doron Bustan ,  Habeeb Farah ,  Thiago Radicchi Roque ,  Felipe Althoff

IPC: G06F11/36 ,  G06N20/00 ,  G06F30/30 ,  G06F30/33 ,  G06F30/333

Abstract: A method for sequential equivalence checking (SEC) of two representations of an electronic design may include using a processor, automatically selecting a plurality of cutpoints in the two representations of the electronic design; using a processor, automatically executing a prove-from strategy on the plurality of cut point pairs to identify a failed cut point pair in the two electronic designs; and using the processor, automatically extending a trace corresponding to the identified failed cut point pair to identify a deeper failed cut point pair or a failed output pair in the two electronic designs.

公开(公告)号：US11151295B1

公开(公告)日：2021-10-19

申请号：US17077187

申请日：2020-10-22

Applicant: Cadence Design Systems, Inc.

Inventor： Doron Bustan ,  Karam Abdelkader ,  Yaron Schiller

IPC: G06F30/3323 ,  G06F30/327

Abstract: A method for enhancing performance of SEC of two representations of an electronic design (with and without gated clock) includes selecting one or more pairs of correlated flip-flops (FFs), a first FF of each pair in the first representation toggled by the gated clock controlled by an enable combinational logic and a second FF of the pair, correlating to the first FF, in the second representation toggled by the constantly toggling clock. The method also includes defining a modified enable combinational logic for the gated clock, as a disjunction of the enable combinational logic of the gated clock and an enable combinational logic for each FF of a plurality of FFs that are toggled by the gated clock. The method also includes performing SEC on the two representations design, using the modified enable combinational logic for the gated clock instead of the enable combinational logic of the gated clock.

公开(公告)号：US10853546B1

公开(公告)日：2020-12-01

申请号：US16583937

申请日：2019-09-26

Applicant: Cadence Design Systems, Inc.

Inventor： Yaron Schiller ,  Almothana Sirhan ,  Karam Abdelkader ,  Habeeb Farah ,  Thiago Radicchi Roque

IPC: G06F30/3323 ,  G06F30/33

Abstract: A method for sequential equivalence checking (SEC) of two representations of an electronic design includes selecting by a processor a plurality of cutpoints in the two representations of the electronic design, rendering the two representations of the electronic design abstracted; executing by the processor an assume-guarantee (AG) proof on the two abstracted representations of the electronic design; identifying by the processor a failed assertion indicating non-equivalence of a signal pair relating to one of the cutpoints; and performing by the processor a simulation on the two representations of the electronic design by successively inputting input stimuli of a trace corresponding to the failed assertion in a sequential order in which the input stimuli appear in the trace at inputs of the two representations of the electronic design to identify whether there is one or a plurality of additional non-equivalent signal pairs relating to other cutpoints of said plurality of cutpoints.