公开(公告)号：US10094875B1

公开(公告)日：2018-10-09

申请号：US15087871

申请日：2016-03-31

Applicant: Cadence Design Systems, Inc.

Inventor： Chien-Liang Lin ,  Andrea Iabrudi Tavares ,  Chung-Wah Norris Ip

IPC: G01R31/317

Abstract: Disclosed are techniques for implementing graph-driven verification and debugging of an electronic design. These techniques identify a pair of interest that comprises a target signal and a clock cycle or an event associated with the target signal from a verification or simulation result of an electronic design or a portion thereof. A boundary for relevant driver identification (RDI) operations may be identified for normal termination of the performance of one or more RDI operations. A debug graph may then be generated and stored at least by performing one or more RDI operations for at least the pair of interest based in whole or in part upon the boundary for RDI operations.

公开(公告)号：US09659142B1

公开(公告)日：2017-05-23

申请号：US14876141

申请日：2015-10-06

Applicant: Cadence Design Systems, Inc.

Inventor： Claudionor Jose Nunes Coelho, Jr. ,  Chung-Wah Norris Ip ,  Thiago Radicchi Roque

IPC: G06F17/50

CPC classification number: G06F17/5022

Abstract: Disclosed are techniques for implementing trace warping for electronic designs. These techniques identify a portion of an electronic design including a set of signals of interest corresponding to a plurality of simulation combinations over a range of clock cycles in a trace display. A pair of matching simulation combinations is identified from one or more pairs of matching simulation combinations for the set of signals of interest; and a first clock cycle and a second clock cycle corresponding to the pair of matching simulation combinations are identified in the range of clock cycles. A plurality of clock cycles between the first clock cycle and the second clock cycle can be compressed in the trace display.

公开(公告)号：US10409945B1

公开(公告)日：2019-09-10

申请号：US14754331

申请日：2015-06-29

Applicant: Cadence Design Systems, Inc.

Inventor： Chung-Wah Norris Ip ,  Georgia Penido Safe ,  Guilherme Henrique de Sousa Santos ,  Adriana Cassia Rossi de Almeida Braz

IPC: G06F17/50

Abstract: Disclosed are techniques for verifying connectivity of an electronic design. These techniques Identify connectivity information for a design description of an electronic design, generate a partition of a plurality of partitions for the connectivity information by partitioning the connectivity into the plurality of partitions based in part or in whole upon one or more factors, and performing a pre-proof verification flow on the partition by proving or disproving at least one connection candidate of a plurality of connection candidates for the partition to generate proof results for the partition. These techniques may further additionally generate a property for a connection candidate that fails to result in definitive proof results and prove or disprove the property with formal methods or techniques.

公开(公告)号：US10162917B1

公开(公告)日：2018-12-25

申请号：US15282936

申请日：2016-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Fabiano Peixoto ,  Benjamin Chen ,  Chung-Wah Norris Ip ,  Björn Håkan Hjort

IPC: G06F17/50

Abstract: Disclosed is an improved approach to implement selective transformations of circuit components for performing verification. The approach looks at the observability of components to downstream properties to determine whether transformations are needed. The verification system leverages the knowledge about the behavior of the domains/components to identify only a subset of components that really need to undergo transformation.

公开(公告)号：US10783304B1

公开(公告)日：2020-09-22

申请号：US16145535

申请日：2018-09-28

Applicant: Cadence Design Systems, Inc.

Inventor： Thiago Radicchi Roque ,  Stefan Staber ,  Chung-Wah Norris Ip

IPC: G06F30/00 ,  G06F30/3323 ,  G06F30/30 ,  G06F111/04

Abstract: The present disclosure relates to a method for electronic design. Embodiments may include displaying, at a graphical user interface, at least a portion of a cover trace or an assertion counter-example associated with an electronic design. Embodiments may also include allowing, at the graphical user interface, a user to analyze the cover trace or the assertion counter-example during a debugging session. Embodiments may further include identifying a dead-end state during the analysis and converting one or more constraints used in the debugging session to soft constraints. Embodiments may further include identifying at least one trace, based upon, at least in part, the soft constraints and displaying at least one unsatisfied constraint associated with the identified trace at the graphical user interface.

公开(公告)号：US10380295B1

公开(公告)日：2019-08-13

申请号：US15087725

申请日：2016-03-31

Applicant: Cadence Design Systems, Inc.

Inventor： Chung-Wah Norris Ip ,  Georgia Penido Safe

IPC: G06F17/50

Abstract: Disclosed are techniques for verifying X-behavior in electronic designs. These techniques identify at least a portion of an electronic design, wherein the at least the portion that includes an input node, an output node, and an internal node located between the input node and the output node. Internal X-propagation proof results may be generated for the internal node based in part or in whole upon an internal precondition and an internal harmless condition for the internal node. X-propagation verification for the output node may then be performed based in part upon one or more assumed properties at the internal node, wherein the one or more assumed properties are assumed at the internal node based in part or in whole upon the internal X-propagation proof results.

公开(公告)号：US10331547B1

公开(公告)日：2019-06-25

申请号：US15602415

申请日：2017-05-23

Applicant: Cadence Design Systems, Inc.

Inventor： Chien-Liang Lin ,  Chung-Wah Norris Ip

IPC: G06F11/00 ,  G06F11/36 ,  G06F17/50

Abstract: The present disclosure relates to a method for reusing a debugging workspace in an electronic design environment. Embodiments may include performing, using a processor, a verification of an electronic design and identifying at least one triggered property associated with the electronic design. Embodiments may further include identifying at least one fan-in signal associated with the at least one triggered property of the electronic design. Embodiments may also include determining a start point debug location based upon, at least in part, the at least one fan-in signal, wherein the start point debug location includes at least one of signal information, cycle information, and event time information. Embodiments may further include generating a debug workspace, wherein generating includes adding at least one additional debug location and storing a cycle of the additional debug location as a relative cycle that is relative to another debug location associated with the debug workspace.

公开(公告)号：US09734278B1

公开(公告)日：2017-08-15

申请号：US14754630

申请日：2015-06-29

Applicant: Cadence Design Systems, Inc.

Inventor： Victor Markus Purri ,  Guilherme Henrique de Sousa Santos ,  Chung-Wah Norris Ip ,  Marcus Vincius da Mata Gomes

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5022 ,  G06F17/504 ,  G06F17/505 ,  G06F2217/84

Abstract: Disclosed are techniques for implementing electronic designs with automatic connectivity information extraction. These techniques traverse at least a portion of an electronic design, classify or categorize circuit component designs encountered during traversal into multiple categories, extract connectivity information for the at least the portion of the electronic design based in part or in whole upon one or more criteria, and devising the at least the portion of the electronic design with at least the connectivity information. A connectivity data structure may be constructed with the extracted connectivity information. A plurality of circuit component designs categorized into the same category may be grouped into a single element in the connectivity data structure.