公开(公告)号：US10331547B1

公开(公告)日：2019-06-25

申请号：US15602415

申请日：2017-05-23

Applicant: Cadence Design Systems, Inc.

Inventor： Chien-Liang Lin ,  Chung-Wah Norris Ip

IPC: G06F11/00 ,  G06F11/36 ,  G06F17/50

Abstract: The present disclosure relates to a method for reusing a debugging workspace in an electronic design environment. Embodiments may include performing, using a processor, a verification of an electronic design and identifying at least one triggered property associated with the electronic design. Embodiments may further include identifying at least one fan-in signal associated with the at least one triggered property of the electronic design. Embodiments may also include determining a start point debug location based upon, at least in part, the at least one fan-in signal, wherein the start point debug location includes at least one of signal information, cycle information, and event time information. Embodiments may further include generating a debug workspace, wherein generating includes adding at least one additional debug location and storing a cycle of the additional debug location as a relative cycle that is relative to another debug location associated with the debug workspace.

公开(公告)号：US10936776B1

公开(公告)日：2021-03-02

申请号：US16834777

申请日：2020-03-30

Applicant: Cadence Design Systems, Inc.

Inventor： Chien-Liang Lin ,  Thamara Karen Cunha Andrade ,  Ronalu Augusta Nunes Barcelos ,  Gabriel Peres Nobre ,  Igor Tiradentes Murta ,  Vitor Machado Guilherme Barros ,  Rafael Sales Medina Ferreira ,  Marcos Augusto de Goes

IPC: G06F30/33 ,  G06F30/333 ,  G06F9/30 ,  G06F8/71 ,  G06F30/20

Abstract: Various embodiments provide for analyzing (e.g., debugging) waveform data generated for a simulated circuit design, which can be used as part of electronic design automation (EDA). For example, where a user modifies a circuit design in a manner that impacts a next simulation run performed on the circuit design, various embodiments perform the next simulation run only on one or more portions of the circuit design affected by the user's modifications, while the results/simulated values for the rest of the circuit design are kept or reused.

公开(公告)号：US10094875B1

公开(公告)日：2018-10-09

申请号：US15087871

申请日：2016-03-31

Applicant: Cadence Design Systems, Inc.

Inventor： Chien-Liang Lin ,  Andrea Iabrudi Tavares ,  Chung-Wah Norris Ip

IPC: G01R31/317

Abstract: Disclosed are techniques for implementing graph-driven verification and debugging of an electronic design. These techniques identify a pair of interest that comprises a target signal and a clock cycle or an event associated with the target signal from a verification or simulation result of an electronic design or a portion thereof. A boundary for relevant driver identification (RDI) operations may be identified for normal termination of the performance of one or more RDI operations. A debug graph may then be generated and stored at least by performing one or more RDI operations for at least the pair of interest based in whole or in part upon the boundary for RDI operations.