公开(公告)号：US10222417B1

公开(公告)日：2019-03-05

申请号：US15362413

申请日：2016-11-28

Applicant: Cadence Design Systems, Inc.

Inventor： Akhil Garg ,  Dale Meehl ,  Sahil Jain

IPC: G01R31/3177 ,  G06F1/08 ,  H04L9/10 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/3183 ,  G01R31/3181 ,  G06F17/50 ,  G11C7/24 ,  G06F11/25 ,  G11C29/32

Abstract: Embodiments relate to providing security of scan mode access and data in an integrated circuit. In embodiments, one or both of two layers of security are provided. A first layer includes requiring a complex initialization sequence to be performed in order to access scan mode. A second layer includes scrambling the scan data before it is output from the circuit under test, which prevents unauthorized persons from extracting useful information from the output scan data. Further embodiments relate to methodologies for utilizing these protection layers after manufacture of the integrated circuit and incorporating these protection layers in an integrated circuit design flow.

公开(公告)号：US08904256B1

公开(公告)日：2014-12-02

申请号：US13673522

申请日：2012-11-09

Applicant: Cadence Design Systems, Inc.

Inventor： Krishna Chakravadhanula ,  Vivek Chickermane ,  Dale Meehl

IPC: G01R31/28 ,  G01R31/3177

CPC classification number: G01R31/318547

Abstract: A method and apparatus to apply compressed test patterns using a very pin-limited test apparatus to a chip design for use in semiconductor manufacturing test is disclosed. Compression circuitry is inserted into the circuit design and the compressed signals manipulated for communication over a serial interface. On a test apparatus, ATPG may be run, assuming a parallel test interface, resulting in test patterns that may be compressed into a parallel format and then converted into a serial signal. On chip, the serial signal is parallelized, decompressed, and then shifted into the scan chains. An inserted controller generates clocks and various control signals. Conventional test patterns from ATPG may be generated and applied during testing without the need to modify the ATPG program saving time and resources. Hierarchical testing of integrated circuits built with a multiplicity of cores, each having its own embedded compression logic, is also supported.

Abstract translation: 公开了一种使用非常针脚限制的测试装置将压缩测试图案应用于用于半导体制造测试中的芯片设计的方法和装置。 压缩电路插入到电路设计中，压缩信号被操纵以通过串行接口进行通信。 在测试装置上，可以运行ATPG，假设为并行测试接口，导致测试模式可能被压缩为并行格式，然后转换为串行信号。 在芯片上，串行信号并行化，解压缩，然后移入扫描链。 插入的控制器产生时钟和各种控制信号。 可以在测试过程中生成和应用ATPG的常规测试模式，而无需修改ATPG程序节省时间和资源。 还支持使用多个内核构建的集成电路的分层测试，每个核心都具有自己的嵌入式压缩逻辑。

公开(公告)号：US08650524B1

公开(公告)日：2014-02-11

申请号：US13673579

申请日：2012-11-09

Applicant: Cadence Design Systems, Inc.

Inventor： Krishna Chakravadhanula ,  Vivek Chickermane ,  Dale Meehl

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F2217/14

Abstract: A method and apparatus to apply compressed test patterns using a very pin-limited test apparatus to a chip design for use in semiconductor manufacturing test is disclosed. Compression circuitry is inserted into the circuit design and the compressed signals manipulated for communication over a serial interface. On a test apparatus, ATPG may be run, assuming a parallel test interface, resulting in test patterns that may be compressed into a parallel format and then converted into a serial signal. On chip, the serial signal is parallelized, decompressed, and then shifted into the scan chains. An inserted controller generates clocks and various control signals. Conventional test patterns from ATPG may be generated and applied during testing without the need to modify the ATPG program saving time and resources. Hierarchical testing of integrated circuits built with a multiplicity of cores, each having its own embedded compression logic, is also supported.