公开(公告)号：US10885250B1

公开(公告)日：2021-01-05

申请号：US16735666

申请日：2020-01-06

Applicant: Cadence Design Systems, Inc.

Inventor： David White ,  Andrew Mark Chapman ,  Thomas Andrew Newton ,  Zhuo Li

IPC: G06F30/3312 ,  G06F30/392 ,  G06F30/396 ,  G06F119/04 ,  G06F117/04

Abstract: Electronic design automation systems, methods, and media are presented for clock gate placement with data path awareness. One embodiment involves accessing a circuit design with a clock tree, clock gates, and an initial movement area. A set of positions for a set of data path connection points associated with the data routing lines are identified, along with an expansion direction from the initial placement position toward the set of positions for the set of data path connection points, and the initial movement is expanded to consider additional placement options for the clock gate based on the data path connection points.

公开(公告)号：US09223925B2

公开(公告)日：2015-12-29

申请号：US14247236

申请日：2014-04-07

Applicant: Cadence Design Systems, Inc.

Inventor： Prakash Krishnan ,  Michael McSherry ,  David White ,  Ed Fischer ,  Bruce Yanagida ,  Keith Dennison

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5068 ,  G06F17/5077

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing electronic designs with simulation awareness. A schematic is identified or created and simulated at the schematic level to characterize the functional behavior of the circuit or to ensure the circuit design meets the required design specifications. Physical data of a component of the design is identified, created, or updated, and the electrical parasitic associated with physical data is characterized. One or more electrical characteristics associated with the parasitic is further characterized and mapped to the simulator to re-simulate the circuit design to analyze the impact of parasitics. Some embodiments re-run the same simulation process incrementally in an interactive manner by accepting incremental design or parameter changes from the design environment.

Abstract translation: 公开了实现具有模拟意识的电子设计的方法，系统和制造。 在原理图级别识别或创建和模拟原理图，以表征电路的功能特性或确保电路设计符合要求的设计规范。 识别，创建或更新设计组件的物理数据，并对与物理数据相关的电子寄存进行表征。 与寄生相关联的一个或多个电特性被进一步表征并映射到仿真器以重新模拟电路设计以分析寄生效应的影响。 一些实施例通过接受来自设计环境的增量设计或参数改变以交互方式递增地重新运行相同的模拟过程。

公开(公告)号：US20140237440A1

公开(公告)日：2014-08-21

申请号：US14247236

申请日：2014-04-07

Applicant: Cadence Design Systems, Inc.

Inventor： Prakash Gopalakrishnan ,  Michael McSherry ,  David White ,  Ed Fischer ,  Bruce Yanagida ,  Keith Dennison

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5068 ,  G06F17/5077

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing electronic designs with simulation awareness. A schematic is identified or created and simulated at the schematic level to characterize the functional behavior of the circuit or to ensure the circuit design meets the required design specifications. Physical data of a component of the design is identified, created, or updated, and the electrical parasitic associated with physical data is characterized. One or more electrical characteristics associated with the parasitic is further characterized and mapped to the simulator to re-simulate the circuit design to analyze the impact of parasitics. Some embodiments re-run the same simulation process incrementally in an interactive manner by accepting incremental design or parameter changes from the design environment.

Abstract translation: 公开了实现具有模拟意识的电子设计的方法，系统和制造。 在原理图级别识别或创建和模拟原理图，以表征电路的功能特性或确保电路设计符合要求的设计规范。 识别，创建或更新设计组件的物理数据，并对与物理数据相关的电子寄存进行表征。 与寄生相关联的一个或多个电特性被进一步表征并映射到仿真器以重新模拟电路设计以分析寄生效应的影响。 一些实施例通过接受来自设计环境的增量设计或参数改变以交互方式递增地重新运行相同的模拟过程。