公开(公告)号：US11645441B1

公开(公告)日：2023-05-09

申请号：US17139657

申请日：2020-12-31

Applicant: Cadence Design Systems, Inc.

Inventor： Bentian Jiang ,  Natarajan Viswanathan ,  Zhuo Li ,  Yi-Xiao Ding

IPC: G06F30/3312 ,  G06N20/00 ,  G06F1/06

CPC classification number: G06F30/3312 ,  G06F1/06 ,  G06N20/00

Abstract: Aspects of the present disclosure address systems and methods for performing a machine-learning based clustering of clock sinks during clock tree synthesis. An integrated circuit (IC) design comprising a clock net that includes a plurality of clock sinks is accessed. An initial number of clusters to generate from the set of clock sinks is determined using a machine-learning model. A first set of clusters is generated from the set of clocks sinks and includes the initial number of clusters. A timing analysis is performed to determine whether each cluster in the first set of clusters satisfies design rule constraints. The initial number of clusters is adjusted based on the timing analysis and a clustering solution is generated based on the adjusted number of clusters.

公开(公告)号：US11526650B1

公开(公告)日：2022-12-13

申请号：US17219761

申请日：2021-03-31

Applicant: Cadence Design Systems, Inc.

Inventor： Yi-Xiao Ding ,  Zhuo Li ,  Jhih-Rong Gao

IPC: G06F30/398 ,  G06F30/392 ,  G06F30/394 ,  G06F30/3308 ,  G06F30/373

Abstract: A system includes one or more processors and a computer storage medium storing instructions that cause a machine to perform operations including accessing an integrated circuit (IC) design including an initial clock tree. The operations include selecting a first driver to evaluate for resizing, the first driver being a first size and having a first leakage current and determining a baseline power consumption measurement of clock tree based on the first size and the first leakage current of the first driver. The operations include identifying a plurality of replacement drivers to replace the first driver and determining a power consumption measurement for a second driver. Based on determining that the power consumption measurement for the second driver is less than the baseline power consumption measurement replacing the first driver with the second driver and generating a layout instance based on the second driver.

公开(公告)号：US11347923B1

公开(公告)日：2022-05-31

申请号：US17219737

申请日：2021-03-31

Applicant: Cadence Design Systems, Inc.

Inventor： Yi-Xiao Ding ,  Zhuo Li ,  Jhih-Rong Gao

IPC: G06F30/392 ,  G06F117/10 ,  G06F111/04

Abstract: An integrated circuit (IC) design is accessed from a database in memory. The IC design comprises an initial buffer tree for a net in the IC design. A maximum cost constraint for rebuffering the net is determined based on the initial buffer tree. A partial rebuffering solution is generated for net and a cost associated with the partial rebuffering solution is determined. Based on determining the cost of the partial rebuffering solution satisfies the maximum cost constraint, the partial rebuffering solution is saved in a set of partial rebuffering solutions for the net. A set of candidate rebuffering solutions for the net is generated based on the set of partial rebuffering solutions, and a rebuffering solution for the net is selected from the set of candidate rebuffering solutions. The database is updated to replace the initial buffer tree in the IC design with the rebuffering solution selected for the net.

公开(公告)号：US10997352B1

公开(公告)日：2021-05-04

申请号：US16416008

申请日：2019-05-17

Applicant: Cadence Design Systems, Inc.

Inventor： Gracieli Posser ,  Mehmet Can Yildiz ,  Wen-Hao Liu ,  Wing-Kai Chow ,  Zhuo Li ,  Derong Liu

IPC: G06F30/394 ,  G06F30/18 ,  G06F30/327

Abstract: Various embodiments provide for routing a network of a circuit design based on at least one of a placement blockage or a layer-assigned network of a circuit design. For instance, some embodiments route a network of a circuit design (e.g., clock net, date net) by generating a congestion map based on modeling layer-assigned networks, considering (e.g., accounting for) routing congestion based on a placement blockage of the circuit design, or some combination of both.

公开(公告)号：US10963620B1

公开(公告)日：2021-03-30

申请号：US16735662

申请日：2020-01-06

Applicant: Cadence Design Systems, Inc.

Inventor： Yi-Xiao Ding ,  Jhih-Rong Gao ,  Zhuo Li

IPC: G06F30/398 ,  G06F30/3947 ,  G06F30/392 ,  G06F30/3953 ,  G06F111/04 ,  G06F117/10

Abstract: Aspects of the present disclosure address improved systems and methods for buffer insertion in an integrated circuit (IC) design using a cost function that accounts for edge spacing and stack via constraints associated with cells in the IC design. An integrated circuit (IC) design comprising a routing topology for a net is accessed. A set of candidate insertion locations along the routing topology are identified. A set of buffering candidates is generated based on the candidate insertion locations. A buffering candidate comprises a cell inserted at a candidate insertion location along the routing topology. A cost associated with the buffering candidate is determined based on a number of potential edge spacing conflicts and a number of stack vias associated with the cell. A buffering solution for the net is selected from the buffering candidate based on the cost associated with the buffering candidate.

公开(公告)号：US10963618B1

公开(公告)日：2021-03-30

申请号：US16735665

申请日：2020-01-06

Applicant: Cadence Design Systems, Inc.

Inventor： Amin Farshidi ,  William Robert Reece ,  Kwangsoo Han ,  Thomas Andrew Newton ,  Zhuo Li

IPC: G06F30/396 ,  G06F30/398 ,  G06F119/12 ,  G06F117/12 ,  G06F119/06 ,  G06F117/04

Abstract: Electronic design automation systems, methods, and media are presented for multi-dimension clock gate design in clock tree synthesis. In one embodiment, an input list of clock gate types is accessed, and the list is then used in generating a clock gate matrix. A circuit design with a clock tree is then accessed. The multi-dimensional design involves automatically selecting, for a first clock gate of the routing tree, a first clock gate type from the clock gate matrix based on a size and associated area for the first clock gate type to select a drive strength value for the first clock gate in the routing tree. The first clock gate is then resized to generate a resized first clock gate using the clock gate matrix to adjust a first delay value associated with the first clock gate while maintaining the drive strength value.

公开(公告)号：US10860757B1

公开(公告)日：2020-12-08

申请号：US16232794

申请日：2018-12-26

Applicant: Cadence Design Systems, Inc.

Inventor： Zhuo Li ,  Michael Alexander

IPC: G06F30/30 ,  G06F119/12

Abstract: Electronic design automation systems, methods, and media are presented for slack scheduling. Some embodiments analyzing slack values at the input and output of a circuit element across multiple views. A skew value is then selected which maximizes the slack at the input and output of the circuit element across all views. In some embodiments, this selection operation is streamlined by first identifying skew ranges that preserve a local worst negative slack, and the selected skew value to maximize the slacks is chosen from the identified skew ranges, in order to limit the computational resources in identifying the skew which maximizes the minimum slack value. An updated circuit design and associated circuitry may then be generated.

公开(公告)号：US10740530B1

公开(公告)日：2020-08-11

申请号：US16228439

申请日：2018-12-20

Applicant: Cadence Design Systems, Inc.

Inventor： Andrew Mark Chapman ,  Zhuo Li

IPC: G06F17/50 ,  G06F30/392 ,  G06F30/3312 ,  G06F30/396 ,  G06F119/06 ,  G06F119/12

Abstract: Aspects of the present disclosure address systems and methods for shortening clock tree wirelength based on target offsets in connected routes. A method may include accessing a clock tree comprising routes that interconnect a plurality of pins. Each pin corresponds to a terminal of a clock tree instance. The method further includes identifying a first and second terminal of a clock tree instance in the clock tree. The method further includes determining a first offset based on a distance between the first terminal and a branch in a first route connected to the first terminal and determining a second offset based on a distance between the second terminal and a branch in a second route connected to the second terminal. The method further includes moving the clock tree instance from a first location to a second location based on a target offset determined by comparing the first and second offsets.

公开(公告)号：US10460064B1

公开(公告)日：2019-10-29

申请号：US15649415

申请日：2017-07-13

Applicant: Cadence Design Systems, Inc.

Inventor： Gracieli Posser ,  Wen-Hao Liu ,  Mehmet Can Yildiz ,  Zhuo Li

IPC: G06F17/50

Abstract: Aspects of the present disclosure address improved systems and methods of partition-aware grid graph based routing for integrated circuit designs. Consistent with some embodiments, a method may include accessing a design layout that defines a layout of components of an integrated circuit design, and includes one or more partitions. The method may further include building a uniform grid graph by superimposing a uniform grid structure over the design layout and inserting additional grid lines into the grid structure such that each partition boundary is aligned with a grid line. The method may further include removing redundant grid lines from the non-uniform grid graph resulting from inserting the additional grid lines, the result of which is the partition-aware grid graph. The method further includes using the partition-aware grid graph to route the integrated circuit design.

公开(公告)号：US10216880B1

公开(公告)日：2019-02-26

申请号：US15212002

申请日：2016-07-15

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Wen-Hao Liu ,  Zhuo Li ,  Charles Alpert ,  Brian Wilson

IPC: G06F17/50

Abstract: Methods and systems of optimization of and Integrated Circuit (IC) design disclosed herein result in a power efficient clustering of circuit devices. The methods may depart from the conventional geometric clustering using a nearest neighbor approach when wiring flops to local clock buffers. To reduce the number of clock-gaters, the methods in one embodiment use a grouping of flops wired to a common clock-gater to form nodes, which are then wired to the local clock buffers based on a load-balancing process. In another embodiment, the methods use a local cleanup process to rewire the nodes between neighboring clock buffers to further reduce the amount of clock-gaters.