公开(公告)号：US10380287B1

公开(公告)日：2019-08-13

申请号：US15638048

申请日：2017-06-29

Applicant: Cadence Design Systems, Inc.

Inventor： Dirk Meyer ,  Zhuo Li ,  Charles Jay Alpert

IPC: G06F17/50

Abstract: Electronic design automation systems, methods, and media are presented for modifying a balanced clock structure. One embodiment involves accessing a circuit design comprising an H-tree clock distribution network that provides a clock signal to a plurality of sinks. Timing requirements for each sink are identified, and a plurality of early tapoff candidate locations are also identified. A corresponding arrival time adjustment associated with each early tapoff candidate location is estimated for early sinks, and an early tapoff location is selected for each early sink based on the early arrival timing requirement and the arrival time adjustment associated with the tapoff location. In various embodiments, different criteria may be used for selecting the early tapoff location, and updated circuit designs are then generated with a route from early sinks to the early tapoff location selected for each early sink.

公开(公告)号：US10706202B1

公开(公告)日：2020-07-07

申请号：US16228473

申请日：2018-12-20

Applicant: Cadence Design Systems, Inc.

Inventor： Dirk Meyer ,  Zhuo Li

IPC: G06F17/50 ,  G06F30/396 ,  G06F30/394 ,  G06F30/3947 ,  G06F30/347 ,  G06F30/398 ,  G06F30/3312 ,  G06F30/337 ,  G06F30/30 ,  G06F30/39 ,  G06F117/10 ,  G06F119/12

Abstract: Systems, methods, media, and other such embodiments described herein relate to generation of routing trees. One embodiment involves accessing a circuit design with a source and a plurality of sinks, and then using a first bottom-up wavefront analysis to select branch point candidates for the sinks. A branch point cost function is used to select among the branch point candidates. This process may be repeated until a final tier of analysis results in a final wavefront that is within a threshold distance of the source. The selected branch points are then used in generating a routing tree between the source and the sinks. In various different embodiments, different cost point functions may be used, and different operations used to manage obstructions or other specific routing considerations.

公开(公告)号：US11321514B1

公开(公告)日：2022-05-03

申请号：US17139612

申请日：2020-12-31

Applicant: Cadence Design Systems, Inc.

Inventor： Dirk Meyer ,  Ben Thomas Beaumont ,  Zhuo Li

IPC: G06F30/396 ,  G06F30/392 ,  G06F111/04

Abstract: Aspects of the present disclosure address systems and methods for clock tree synthesis (CTS). A first iteration of CTS is performed to generate an intermediate clock tree for an integrated circuit (IC) design that includes one or more macros. Target pin insertion delays (PIDs) for the one or more macros are computed based on the intermediate clock tree using a linear program. A second iteration of CTS is performed using the target PIDs for the one or more macros to generate an optimized clock tree for the IC design.

公开(公告)号：US10929589B1

公开(公告)日：2021-02-23

申请号：US16823998

申请日：2020-03-19

Applicant: Cadence Design Systems, Inc.

Inventor： Dirk Meyer ,  Zhuo Li

IPC: G06F30/00 ,  G06F30/396 ,  G06F30/394 ,  G06F30/31

Abstract: Various embodiments provide for generating a routing structure for a clock network based on edge interaction detection, which can facilitate detection/consideration of overuse of routing resources to a balanced routing structure and which may be part of electronic design automation (EDA) of a circuit design. For example, some embodiments use an edge intersection check to detect overuse of routing resources within the routing structure for a clock network.

公开(公告)号：US10282506B1

公开(公告)日：2019-05-07

申请号：US15688725

申请日：2017-08-28

Applicant: Cadence Design Systems, Inc.

Inventor： Dirk Meyer ,  Zhuo Li ,  Charles Jay Alpert

IPC: G06F1/10 ,  G06F17/50

Abstract: Systems, methods, media, and other such embodiments described herein relate to generation of clock routing trees. One embodiment involves accessing a circuit design and a clock tree hierarchy input indicating a nested list of partition or sink groups, each group of the nested list of groups comprising one or more clock tree elements of a plurality of clock tree elements from the circuit design. A routing topology associated with a source and a plurality of sinks are determined based on an ordering within the nested list of partition groups. These routing directions are used in synthesizing a clock tree for the circuit design. In additional embodiments, the clock tree hierarchy input provides clustering information, port placement for connections between partition groups of the clock tree, and parameters describing limitations or criteria for individual partition groups.