公开(公告)号：US10289798B1

公开(公告)日：2019-05-14

申请号：US15718511

申请日：2017-09-28

Applicant: Cadence Design Systems, Inc.

Inventor： Ronalu Augusta Nunes Barcelos ,  Hudson Dyele Pinheiro de Oliveira ,  Mirlaine Aparecida Crepalde ,  Lucas Luz Reckziegel ,  Glauber Tadeu de Sousa Carmo ,  Augusto Amaral Mafra ,  Regina Mara Amaral Fonseca ,  Guilherme Henrique de Sousa Santos ,  Valdir Antoniazzi Júnior

IPC: G06F17/50 ,  G06N20/00

Abstract: The present disclosure relates to a method for debugging associated with formal verification of an electronic design. Embodiments may include performing, using a processor, an initial formal verification of an electronic design. Embodiments may further include identifying one or more counter-examples associated with one or more assertion properties of the electronic design or identifying one or more cover-traces associated with one or more cover properties of the electronic design. Embodiments may further include generating a trace core for each of the one or more counter-examples or cover-traces, wherein each trace core includes a minimal representation of the counter-example or cover-trace. Embodiments may further include identifying a similarity between a plurality of the trace cores and clustering the plurality of trace cores having the similarity.