公开(公告)号：US10289798B1

公开(公告)日：2019-05-14

申请号：US15718511

申请日：2017-09-28

Applicant: Cadence Design Systems, Inc.

Inventor： Ronalu Augusta Nunes Barcelos ,  Hudson Dyele Pinheiro de Oliveira ,  Mirlaine Aparecida Crepalde ,  Lucas Luz Reckziegel ,  Glauber Tadeu de Sousa Carmo ,  Augusto Amaral Mafra ,  Regina Mara Amaral Fonseca ,  Guilherme Henrique de Sousa Santos ,  Valdir Antoniazzi Júnior

IPC: G06F17/50 ,  G06N20/00

Abstract: The present disclosure relates to a method for debugging associated with formal verification of an electronic design. Embodiments may include performing, using a processor, an initial formal verification of an electronic design. Embodiments may further include identifying one or more counter-examples associated with one or more assertion properties of the electronic design or identifying one or more cover-traces associated with one or more cover properties of the electronic design. Embodiments may further include generating a trace core for each of the one or more counter-examples or cover-traces, wherein each trace core includes a minimal representation of the counter-example or cover-trace. Embodiments may further include identifying a similarity between a plurality of the trace cores and clustering the plurality of trace cores having the similarity.

公开(公告)号：US10540467B1

公开(公告)日：2020-01-21

申请号：US15943819

申请日：2018-04-03

Applicant: Cadence Design Systems, Inc.

Inventor： Craig Franklin Deaton ,  Abner Luis Panho Marciano ,  Matheus Nogueira Fonseca ,  Ronalu Augusta Nunes Barcelos ,  Fabiano Cruz Peixoto

IPC: G06F17/50

Abstract: The present disclosure relates to a method for electronic circuit design. Embodiments may include receiving, using a processor, an electronic circuit design and identifying at least one combinational loop associated with the electronic circuit design. Embodiments may also include extracting, for each component of the loop, a set of logic conditions and modeling the at least one combinational loop. Embodiments may further include providing a graphical user interface configured to display one or more constraint candidates and determining whether or not a conflict exists between constraint candidates. Embodiments may also include ranking the constraint candidates, based upon, at least in part, a number of loops disabled and one or more disabled loop characteristics.

公开(公告)号：US10936776B1

公开(公告)日：2021-03-02

申请号：US16834777

申请日：2020-03-30

Applicant: Cadence Design Systems, Inc.

Inventor： Chien-Liang Lin ,  Thamara Karen Cunha Andrade ,  Ronalu Augusta Nunes Barcelos ,  Gabriel Peres Nobre ,  Igor Tiradentes Murta ,  Vitor Machado Guilherme Barros ,  Rafael Sales Medina Ferreira ,  Marcos Augusto de Goes

IPC: G06F30/33 ,  G06F30/333 ,  G06F9/30 ,  G06F8/71 ,  G06F30/20

Abstract: Various embodiments provide for analyzing (e.g., debugging) waveform data generated for a simulated circuit design, which can be used as part of electronic design automation (EDA). For example, where a user modifies a circuit design in a manner that impacts a next simulation run performed on the circuit design, various embodiments perform the next simulation run only on one or more portions of the circuit design affected by the user's modifications, while the results/simulated values for the rest of the circuit design are kept or reused.