公开(公告)号：US10706195B1

公开(公告)日：2020-07-07

申请号：US15989469

申请日：2018-05-25

Applicant: Cadence Design Systems, Inc.

Inventor： Luis Humberto Rezende Barbosa ,  Raquel Lara dos Santos Pereira ,  Caio Alves Furtado ,  Breno Augusto Dias Vitorino ,  Mirlaine Aparecida Crepalde ,  Rodrigo da Silva Mantini Viana ,  Lucas Duarte Prates

IPC: G06F17/50 ,  G06F30/3323 ,  G06F30/30 ,  G06F30/31 ,  G06F30/367 ,  G06F30/337 ,  G06F30/373 ,  G06F30/398

Abstract: The present disclosure relates to a method for use in the formal verification of an electronic circuit. Embodiments may include receiving, using a processor, a portion of an electronic circuit design and analyzing a syntactic structure of a string associated with the electronic circuit design. Embodiments may also include generating a parse tree, based upon, at least in part, the analysis and traversing the parse tree to identify one or more conditional nodes. Embodiments may further include generating a new node for each of the one or more conditional nodes and displaying, at a graphical user interface, a check, at least one of the one or more conditional nodes or the new node prior to performing either register-transfer-level RTL synthesis or final synthesis.

公开(公告)号：US10956640B1

公开(公告)日：2021-03-23

申请号：US16507574

申请日：2019-07-10

Applicant: Cadence Design Systems, Inc.

Inventor： Georgia Penido Safe ,  Mirlaine Aparecida Crepalde ,  Yumi Monma ,  Felipe Althoff ,  Fernanda Augusta Braga ,  Lucas Martins Chaves ,  Pedro Bruno Neri Silva ,  Mariana Ferreira Marques ,  Vincent Gregory Reynolds

IPC: G06F17/50 ,  G06F30/3323 ,  G06K9/62 ,  G06N20/00

Abstract: The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using a processor, an electronic design and providing at least a portion of the electronic design to a machine learning engine. Embodiments may further include automatically determining, based upon, at least in part, an output of the machine learning engine whether or not the at least a portion of the electronic design is amenable to formal verification.

公开(公告)号：US10289798B1

公开(公告)日：2019-05-14

申请号：US15718511

申请日：2017-09-28

Applicant: Cadence Design Systems, Inc.

Inventor： Ronalu Augusta Nunes Barcelos ,  Hudson Dyele Pinheiro de Oliveira ,  Mirlaine Aparecida Crepalde ,  Lucas Luz Reckziegel ,  Glauber Tadeu de Sousa Carmo ,  Augusto Amaral Mafra ,  Regina Mara Amaral Fonseca ,  Guilherme Henrique de Sousa Santos ,  Valdir Antoniazzi Júnior

IPC: G06F17/50 ,  G06N20/00

Abstract: The present disclosure relates to a method for debugging associated with formal verification of an electronic design. Embodiments may include performing, using a processor, an initial formal verification of an electronic design. Embodiments may further include identifying one or more counter-examples associated with one or more assertion properties of the electronic design or identifying one or more cover-traces associated with one or more cover properties of the electronic design. Embodiments may further include generating a trace core for each of the one or more counter-examples or cover-traces, wherein each trace core includes a minimal representation of the counter-example or cover-trace. Embodiments may further include identifying a similarity between a plurality of the trace cores and clustering the plurality of trace cores having the similarity.