公开(公告)号：US11082267B1

公开(公告)日：2021-08-03

申请号：US16904019

申请日：2020-06-17

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Vinod Kumar ,  Harsh Anil Shakrani ,  Balbeer Rathor

IPC: H04L25/03 ,  G11C7/10

Abstract: The embodiments described herein provide for a method and system for implementing a multi-tap hybrid-equalization technique devoid of ISI jitter and PSI jitter in the high-speed data path to achieve 24 Gbps operating speed in systems utilizing GDDR6 DRAM. The method includes receiving an original data signal at a first TFFE circuit and receiving an altered data signal at a second TFFE circuit. The method further comprises generating a time-domain-equalized original data signal using a set of TFFE coefficients from the original data signal. The method further comprises generating a time-domain-equalized altered data signal using the set of TFFE coefficients from the altered data signal. The method further comprises generating, a time-and-voltage-domain-equalized data signal from the time-domain-equalized original data signal and the time-domain-equalized altered data signal at a voltage-feed forward equalization (VFFE) circuit using a set of VFFE coefficients.

公开(公告)号：US12040798B1

公开(公告)日：2024-07-16

申请号：US17731387

申请日：2022-04-28

Applicant: Cadence Design Systems, Inc.

Inventor： Vinod Kumar ,  Prakash Kumar Lenka ,  Harsh Anil Shakrani

IPC: G11C11/4076 ,  G06F1/10 ,  G11C11/409 ,  H03K3/011 ,  H03K3/012

CPC classification number: H03K3/011 ,  G06F1/10 ,  G11C11/4076 ,  G11C11/409 ,  H03K3/012

Abstract: Embodiments included herein are directed towards a voltage-temperature drift resistant and power efficient clock distribution circuit. Embodiments may include a current generator and a voltage generator configured to receive an input from the current generator. Embodiments may also include a regulator which may be configured to receive a reference voltage from the voltage generator as an input and to generate regulated voltage as output. The clock distribution path may operate on a regulated voltage, the regulated voltage having a value proportional to a threshold value associated with a plurality of devices included in the clock distribution path.