公开(公告)号：US12212315B1

公开(公告)日：2025-01-28

申请号：US18093281

申请日：2023-01-04

Applicant: Cadence Design Systems, Inc.

Inventor： Vinod Kumar

IPC: G11C5/14 ,  H03K3/011 ,  H03K17/687 ,  G11C11/4093

Abstract: Methods and systems are provided for transmitting data using thin-oxide devices. The methods and system generate a first bias voltage and a second bias voltage based on a power supply voltage of the second voltage domain, the first bias voltage value representing a high-level voltage signal of the first voltage domain, and the second bias voltage representing a low-level voltage signal of the second voltage domain and its value corresponds to a difference between the second voltage domain and the first voltage domain. The methods and systems generate an output of the thin-oxide device interface using first and second thin-oxide devices, the output of the thin-oxide device interface having a range corresponding to the second voltage domain.

公开(公告)号：US11677593B1

公开(公告)日：2023-06-13

申请号：US17752829

申请日：2022-05-24

Applicant: Cadence Design Systems, Inc.

Inventor： Vinod Kumar ,  Thomas Evan Wilson

IPC: H04L25/03

CPC classification number: H04L25/03057

Abstract: Various embodiments provide for a data sampler with built-in decision feedback equalization (DFE) and offset cancellation. For some embodiments, two or more data samplers described herein can be used to implement a data signal receiver circuit, which can use those two or more data samplers to facilitate half-rate or quarter-rate data sampling.

公开(公告)号：US10164524B1

公开(公告)日：2018-12-25

申请号：US15169505

申请日：2016-05-31

Applicant: Cadence Design Systems, Inc.

Inventor： Vinod Kumar ,  Tara Vishin

IPC: H02M3/155 ,  G11C7/20 ,  G06F1/32 ,  G11C11/4074

Abstract: Embodiments relate to circuits, electronic design assistance (EDA) circuit layouts, systems, methods, and computer readable media to enable logic devices operating on a core supply voltage to drive memory devices operating on different supply voltages. In one embodiment, a programmable level translator device is implemented using an NMOS transistor pair and a PMOS cross quad. The switching characteristics are modified with the use of a charge pump connected to the gate terminals of two of the PMOS transistors within the PMOS cross quad. Transmission gates are also employed to engage and disengage the charge pump based on a control switch. In various embodiments, the level translator device works with a number of memory devices operating over a wide range of power supply voltages.

公开(公告)号：US11874788B1

公开(公告)日：2024-01-16

申请号：US17848725

申请日：2022-06-24

Applicant: Cadence Design Systems, Inc.

Inventor： Vinod Kumar

IPC: G06F13/40 ,  H03K19/1776 ,  H03K19/017 ,  G06F13/16

CPC classification number: G06F13/4072 ,  G06F13/1689 ,  H03K19/01742 ,  H03K19/1776

Abstract: Embodiments included herein are directed towards a transmitter circuit. The circuit may include a most significant bit (“MSB”) main driver and a most significant bit boost driver operatively connected to the MSB main driver. The circuit may also include a least significant bit (“LSB”) main driver and a least significant bit boost driver operatively connected to the LSB main driver, wherein the MSB main driver and the LSB main driver are configured to receive two parallel non-return-to-zero (“NRZ”) data inputs.

公开(公告)号：US11481148B1

公开(公告)日：2022-10-25

申请号：US17362352

申请日：2021-06-29

Applicant: Cadence Design Systems, Inc.

Inventor： Vinod Kumar ,  Hajee Mohammed Shuaeb Fazeel ,  Thomas Evan Wilson

IPC: G06F3/06 ,  H03K17/0412

Abstract: This disclosure relates to slew rate boosting for communication interfaces. A circuit can include a driver circuit coupled to an output node and configured to provide a data signal to the output node based on an input signal. The data signal can a similar logical state as the input signal. The circuit can include a signal transition boosting circuit coupled to the output node and configured to provide a boosting signal to the output node based on the input signal and a charge pump delay adjustment signal. The charge pump delay adjustment signal can define an amount of time after which the boosting signal is provided to the output node. The boosting signal can be provided to the output node to signal boost the data signal for the amount of time defined by the charge pump delay adjustment signal to provide a boosted data signal at the output node.

公开(公告)号：US09754646B1

公开(公告)日：2017-09-05

申请号：US15342974

申请日：2016-11-03

Applicant: Cadence Design Systems, Inc.

Inventor： Vinod Kumar ,  Tara Vishin ,  Sachin Ramesh Gugwad ,  Thomas Evan Wilson

IPC: G11C7/12 ,  G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1012 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1084 ,  G11C7/1093

Abstract: Embodiments relate to circuits, electronic design automation (EDA) circuit layouts, systems, methods, and computer readable media to enable logic devices operating on a core supply voltage to drive memory devices operating on a different supply voltage using low power and high data rates while avoiding voltage over-stress of thin-oxide transistors. In an embodiment, channels of a thin-oxide PMOS transistor, a thick-oxide PMOS transistor, a thick-oxide NMOS transistor, and a thin-oxide NMOS transistor are coupled in order from a memory device voltage supply rail to a low voltage supply rail. Gates of the thin-oxide PMOS transistor and the thick-oxide NMOS transistor are coupled with an output of a flying capacitor circuit that level-shifts an input signal by a difference between the memory device supply and core supply voltages, while gates of the thick-oxide PMOS transistor and the thin-oxide NMOS transistor receive the input signal via a buffer.

公开(公告)号：US12107578B1

公开(公告)日：2024-10-01

申请号：US18075117

申请日：2022-12-05

Applicant: Cadence Design Systems, Inc.

Inventor： Vinod Kumar

IPC: H03L5/00 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/0185

CPC classification number: H03K19/018521

Abstract: Methods and systems are provided for performing voltage level shifting using thin-oxide devices. The methods and systems convert an input signal associated with a first voltage domain to output signals associated with the first and second voltage domains. A first set of thin-oxide devices generate a first output signal at the high-level voltage signal when the input signal comprises a high logic level and generate the first output signal at a ground level voltage signal when the input signal comprises a low logic level. A second set of thin-oxide devices generate a second output signal at a power supply voltage level of the second voltage domain when the input signal comprises the high logic level and generate the second output signal at the second bias voltage when the input signal comprises the low logic level.

公开(公告)号：US12040798B1

公开(公告)日：2024-07-16

申请号：US17731387

申请日：2022-04-28

Applicant: Cadence Design Systems, Inc.

Inventor： Vinod Kumar ,  Prakash Kumar Lenka ,  Harsh Anil Shakrani

IPC: G11C11/4076 ,  G06F1/10 ,  G11C11/409 ,  H03K3/011 ,  H03K3/012

CPC classification number: H03K3/011 ,  G06F1/10 ,  G11C11/4076 ,  G11C11/409 ,  H03K3/012

Abstract: Embodiments included herein are directed towards a voltage-temperature drift resistant and power efficient clock distribution circuit. Embodiments may include a current generator and a voltage generator configured to receive an input from the current generator. Embodiments may also include a regulator which may be configured to receive a reference voltage from the voltage generator as an input and to generate regulated voltage as output. The clock distribution path may operate on a regulated voltage, the regulated voltage having a value proportional to a threshold value associated with a plurality of devices included in the clock distribution path.

公开(公告)号：US11568923B1

公开(公告)日：2023-01-31

申请号：US17352938

申请日：2021-06-21

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Hajee Mohammed Shuaeb Fazeel ,  Vinod Kumar

IPC: G11C11/24 ,  G11C11/4093 ,  H03F3/45

Abstract: A device, a memory interface device, and a method of implementing an active inductor circuit are disclosed. In one aspect, the device includes one or more active inductor circuits, each including a first metal-oxide-semiconductor (MOS) transistor and a second MOS transistor. The first MOS transistor has a first terminal connected to a first voltage level, a second terminal connected to a resistor, and a gate terminal. The second MOS transistor has a first terminal connected to the first voltage level, a second terminal connected to a first current source and the gate terminal of the first MOS transistor, and a gate terminal connected to the resistor and to a capacitor connected to a second voltage level. One of the first MOS transistor and the second MOS transistor is a p-channel MOS (PMOS) transistor, and another of the first MOS transistor and the second MOS transistor is an n-channel MOS (NMOS) transistor.

公开(公告)号：US10566046B1

公开(公告)日：2020-02-18

申请号：US16175577

申请日：2018-10-30

Applicant: Cadence Design Systems, Inc.

Inventor： Vinod Kumar ,  Thomas E. Wilson ,  Hari Anand Ravi

IPC: H03K3/00 ,  G11C11/4093 ,  H03K3/57 ,  H03K17/687

Abstract: Implementations described herein relate to circuits and techniques increasing transmitter output speed. In some implementations, a circuit is described using a pull-up data path comprising a first flying capacitor, a first buffer, a thin-oxide PMOS device, and a thick-oxide PMOS device, a pull-down data path comprising a second flying capacitor, a second buffer, a thin-oxide NMOS device, and a thick-oxide NMOS device, wherein the pull-up data path and the pull-down data path are operatively connected to a core data output signal line.