公开(公告)号：US12184286B1

公开(公告)日：2024-12-31

申请号：US17831685

申请日：2022-06-03

Applicant: Cadence Design Systems, Inc.

Inventor： Prakash Kumar Lenka ,  Hari Anand Ravi ,  Jitendra Kumar Yadav

IPC: H03K5/00 ,  G01R29/02 ,  H03K3/017 ,  H03K5/24

Abstract: The present disclosure describes a circuit that may include a first amplifier portion configured to receive a first input signal corresponding to a first clock signal and a second input signal corresponding to a second clock signal. The circuit may include a first amplifier of the first amplifier portion. The first amplifier may be configured to receive a first amplifier input signal and a second amplifier input signal. The circuit may include a second amplifier portion configured to receive a first output signal from the first amplifier portion. In a first mode, the first amplifier input signal may be based upon the second input signal and the second amplifier input signal may be based upon the first input signal. In a second mode, the first amplifier input signal may be based upon the first input signal and the second amplifier input signal may be based upon the second input signal.

公开(公告)号：US12040798B1

公开(公告)日：2024-07-16

申请号：US17731387

申请日：2022-04-28

Applicant: Cadence Design Systems, Inc.

Inventor： Vinod Kumar ,  Prakash Kumar Lenka ,  Harsh Anil Shakrani

IPC: G11C11/4076 ,  G06F1/10 ,  G11C11/409 ,  H03K3/011 ,  H03K3/012

CPC classification number: H03K3/011 ,  G06F1/10 ,  G11C11/4076 ,  G11C11/409 ,  H03K3/012

Abstract: Embodiments included herein are directed towards a voltage-temperature drift resistant and power efficient clock distribution circuit. Embodiments may include a current generator and a voltage generator configured to receive an input from the current generator. Embodiments may also include a regulator which may be configured to receive a reference voltage from the voltage generator as an input and to generate regulated voltage as output. The clock distribution path may operate on a regulated voltage, the regulated voltage having a value proportional to a threshold value associated with a plurality of devices included in the clock distribution path.