公开(公告)号：US11513818B1

公开(公告)日：2022-11-29

申请号：US16948771

申请日：2020-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Rong Chen ,  He Xiao ,  Nenad Nedeljkovic ,  Nupur B. Andrews ,  Dan Nicolaescu ,  James Sangkyu Kim

IPC: G06F9/445 ,  G06F8/41

Abstract: An approach includes the use of a description of instructions for invoking hardware accelerator and for a hardware accelerator to execute those instructions. In some embodiments, the instructions for invoking hardware accelerator and for a hardware accelerator to execute those instructions are described using a single language. These descriptions are then compiled into other languages for use in tool chains for generating simulators (a hardware and instruction set simulator and a hardware accelerator simulator). In some embodiments, the approach illustrated herein can be combined with state machine functionality to manage the execution of instructions that require multiple states. In some embodiments, the approach illustrated herein can be combined with an external register file for transferring information between a processor and a hardware accelerator.