公开(公告)号：US11513818B1

公开(公告)日：2022-11-29

申请号：US16948771

申请日：2020-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Rong Chen ,  He Xiao ,  Nenad Nedeljkovic ,  Nupur B. Andrews ,  Dan Nicolaescu ,  James Sangkyu Kim

IPC: G06F9/445 ,  G06F8/41

Abstract: An approach includes the use of a description of instructions for invoking hardware accelerator and for a hardware accelerator to execute those instructions. In some embodiments, the instructions for invoking hardware accelerator and for a hardware accelerator to execute those instructions are described using a single language. These descriptions are then compiled into other languages for use in tool chains for generating simulators (a hardware and instruction set simulator and a hardware accelerator simulator). In some embodiments, the approach illustrated herein can be combined with state machine functionality to manage the execution of instructions that require multiple states. In some embodiments, the approach illustrated herein can be combined with an external register file for transferring information between a processor and a hardware accelerator.

公开(公告)号：US09250900B1

公开(公告)日：2016-02-02

申请号：US14503410

申请日：2014-10-01

Applicant: Cadence Design Systems, Inc.

Inventor： James Sangkyu Kim ,  Fei Sun ,  Kyle Satoshi Tsukamoto

IPC: G06F17/50 ,  G06F9/30 ,  G06F15/76

CPC classification number: G06F15/76 ,  G06F17/5045 ,  G06F2217/68

Abstract: Methods and systems for implementing a microprocessor with a selective register file bypass network are disclosed. Late bypasses are removed from a register file bypass network of a microprocessor design. One or more late bypasses are then added back to the register file bypass network based at least in part upon the results of analyzing a plurality of instructions that are to be processed in an instruction pipeline of the microprocessor. An electronic design for at least the register file bypass network is then generated with these one or more late bypasses that are added to the register file bypass network. Without incurring additional hardware or cost for the microprocessor design, one or more bypasses in the register file bypass network may be optionally shared among multiple free-riders, and an entire port stage may also be optionally bypassed to another port stage based upon one or more criteria.

Abstract translation: 公开了一种用于实现具有选择性寄存器文件旁路网络的微处理器的方法和系统。 延迟旁路从微处理器设计的寄存器文件旁路网络中删除。 至少部分地基于在微处理器的指令流水线中分析要处理的多个指令的结果，一个或多个后期旁路被添加回寄存器文件旁路网络。 然后，通过添加到寄存器文件旁路网络的这些一个或多个延迟旁路来生成至少寄存器文件旁路网络的电子设计。 不会对微处理器设计造成额外的硬件或成本，寄存器文件旁路网络中的一个或多个旁路可以可选地在多个自由车间共享，并且整个端口级还可以根据一个或多个可选地绕过另一个端口级 标准