公开(公告)号：US11063614B1

公开(公告)日：2021-07-13

申请号：US16690575

申请日：2019-11-21

Applicant: Cadence Design Systems, Inc.

Inventor： Rong Chen ,  Poojan Rajeshbhai Shah ,  Dan Nicolaescu

IPC: H03M13/45 ,  H03M13/13

Abstract: In some examples, a polar decoder for implementing polar decoding of a codeword can be configured to implement alogarithmic likelihood ratio (LLR), an even bit, and an odd bit buffer, respectively. The polar decoder can be configured to employ a list-to-buffer mapping state register for the LLR buffer for loading LLR values for each path at a given stage of a decoding graph. The polar decoder can be configured to update and store LLR values for each path at the given stage. The polar decoder can be configured to employ a list-to-buffer mapping state register for the even bit buffer for loading even bit values from the even bit buffer and loading odd bit values from the odd bit buffer, and updating even or odd bit values for each path at the given stage of the decoding graph.

公开(公告)号：US09619205B1

公开(公告)日：2017-04-11

申请号：US14295818

申请日：2014-06-04

Applicant: Cadence Design Systems, Inc.

Inventor： Christopher Rowen ,  Teodur Doru Cuturela ,  Xiaoguang Lv ,  Dan Nicolaescu ,  Pushkar Patwardhan ,  Manish Ashok Paradkar ,  Pranava Tummala

IPC: G06F7/483

CPC classification number: G06F7/483

Abstract: A computer implemented method for performing floating point operations as part of a processor architecture that also includes fixed point operations is disclosed. The computer implemented method includes providing a group of instructions within the fixed point architecture. A floating point value is split between two programmer visible registers. In a system and method in accordance with the present invention a new form of floating point representation and associated processor operations, including efficient complex number representations and operations are utilized.

公开(公告)号：US11513818B1

公开(公告)日：2022-11-29

申请号：US16948771

申请日：2020-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Rong Chen ,  He Xiao ,  Nenad Nedeljkovic ,  Nupur B. Andrews ,  Dan Nicolaescu ,  James Sangkyu Kim

IPC: G06F9/445 ,  G06F8/41

Abstract: An approach includes the use of a description of instructions for invoking hardware accelerator and for a hardware accelerator to execute those instructions. In some embodiments, the instructions for invoking hardware accelerator and for a hardware accelerator to execute those instructions are described using a single language. These descriptions are then compiled into other languages for use in tool chains for generating simulators (a hardware and instruction set simulator and a hardware accelerator simulator). In some embodiments, the approach illustrated herein can be combined with state machine functionality to manage the execution of instructions that require multiple states. In some embodiments, the approach illustrated herein can be combined with an external register file for transferring information between a processor and a hardware accelerator.