公开(公告)号：US12141233B1

公开(公告)日：2024-11-12

申请号：US16587790

申请日：2019-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Marco Tony Lloyd Kassis ,  Mina Adel Aziz Farhan ,  Joel Reuben Phillips

IPC: G06F18/214 ,  G06F17/12 ,  G06F17/14 ,  G06N20/00

Abstract: Disclosed are methods, systems, and articles of manufacture for characterizing an electronic design with an MOR-based envelope Fourier technique. Multiple training models may be determined at multiple time points for an electronic circuit by using at least the MOR-based envelope Fourier technique that comprises a harmonic balance technique. A training model of the multiple training models may be reduced into a reduced order training model in a reduced order space at least by applying at least model order reduction of the MOR-based envelope Fourier technique to the training model. A time varying system may be determined for the electronic circuit based by using at least the reduced order training model.

公开(公告)号：US10860767B1

公开(公告)日：2020-12-08

申请号：US15860382

申请日：2018-01-02

Applicant: Cadence Design Systems, Inc.

Inventor： Mina Adel Aziz Farhan ,  Joel R. Phillips

IPC: G06F30/367 ,  G06F17/11 ,  G06F17/16 ,  G06F17/13

Abstract: Various embodiments describe performing a transient simulation of circuits that have mutual inductors. In particular, some embodiments perform a transient simulation on a circuit model by removing and approximating the effects of one or more entries of a matrix in the circuit model, where the matrix relates to inductors or mutual inductors of the circuit. In doing so, such embodiments can render the matrix more sparse than before which, in turn, can reduce the time spent during the transient simulation to solve equations of the circuit model.