公开(公告)号：US11868698B1

公开(公告)日：2024-01-09

申请号：US17541171

申请日：2021-12-02

Applicant: Cadence Design Systems, Inc.

Inventor： Joshua David Tygert ,  Jonathan R. Fales ,  Rwik Sengupta ,  Timothy H. Pylant

IPC: G06F30/392 ,  G06F30/31 ,  G06F30/398

CPC classification number: G06F30/392 ,  G06F30/31 ,  G06F30/398

Abstract: Various embodiments provide for context-aware circuit design layout construct, which may be part of electronic design automation (EDA). In particular, some embodiments enable use of a circuit design layout construct with a layout of a circuit design (hereafter, a circuit design layout), where a programmable pattern of layout shapes of the circuit design layout construct can be inserted into a circuit design layout and can be adapted based on context information associated with the location of its placement within the circuit design layout.

公开(公告)号：US11803684B1

公开(公告)日：2023-10-31

申请号：US17493550

申请日：2021-10-04

Applicant: Cadence Design Systems, Inc.

Inventor： Jonathan R. Fales ,  Joshua David Tygert

IPC: G06F30/00 ,  G06F30/392 ,  G06F30/3947 ,  G06F30/39 ,  H04L41/0897 ,  G06T3/40

CPC classification number: G06F30/392 ,  G06F30/39 ,  G06F30/3947 ,  H04L41/0897 ,  G06T3/40

Abstract: Various embodiments described herein provide for a method and system for relative placement of components for a circuit layout by retrieving a data structure of a first circuit design, the data structure including a location of each component, determining a component characteristic for each component, and selecting a first group of two or more components having a shared component characteristic. Additionally, the method and system can instantiate a second circuit design and retrieve the data structure after the second circuit design is instantiated. The method and system include, for the second circuit design, calculating a first scaling factor and scaling each of the components of the first group from the first circuit design and placing the first group at a location in the second circuit design corresponding to location of the first group within the first circuit design.

公开(公告)号：US11354470B1

公开(公告)日：2022-06-07

申请号：US17173440

申请日：2021-02-11

Applicant: Cadence Design Systems, Inc.

Inventor： Jonathan Robert Fales ,  Joshua David Tygert ,  Rwik Sengupta ,  Timothy H. Pylant

IPC: G06F30/31

Abstract: Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving, using a processor, an initial data set associated with an electronic design and performing a built in self-discovery (BISD) analysis based upon, at least in part, the initial data set. Embodiments may include displaying, at a graphical user interface, a plurality of tiered, user-selectable options and receiving a user input corresponding to a selection of at least one of the plurality of tiered, user selectable options. Embodiments may also include tuning the plurality of tiered user selectable options based upon, at least in part, the user input.