公开(公告)号：US11797747B1

公开(公告)日：2023-10-24

申请号：US17410837

申请日：2021-08-24

Applicant: Cadence Design Systems, Inc.

Inventor： Matthew David Eaton ,  George Simon Taylor ,  Zhuo Li ,  James Youren ,  Ji Xu

IPC: G06F9/455 ,  G06F30/398 ,  G06F117/04

CPC classification number: G06F30/398 ,  G06F2117/04

Abstract: Various embodiments provide for determining redundant logic in a circuit design based on one or more enable conditions of clock gates, which can be part of electronic design automation (EDA). In particular, some embodiments use one or more enable conditions (of the clock gates) with a satisfiability solver to determine redundant logic coupled to clock circuit elements gated by the clock gates.

公开(公告)号：US11354480B1

公开(公告)日：2022-06-07

申请号：US17360782

申请日：2021-06-28

Applicant: Cadence Design Systems, Inc.

Inventor： Matthew David Eaton ,  Ji Xu ,  George Simon Taylor ,  Zhuo Li

IPC: G06F30/396 ,  G06F30/3308 ,  G06F30/3312 ,  G06F30/3323 ,  G06F30/367 ,  G06F30/398

Abstract: Various embodiments provide for determining clock gates for decloning based on simulation and a satisfiability solver, which can be part of electronic design automation (EDA). In particular, some embodiments use a simulation process to quickly determine whether enable signals associated with two clock gates are logically equivalent using a random input vector to a circuit design and, if logically equivalent by the simulation process, use a satisfiability solver to determine a variable assignment (e.g., at least one vector) such that the enable signals are found to be non-equivalent.

公开(公告)号：US10997336B1

公开(公告)日：2021-05-04

申请号：US16181533

申请日：2018-11-06

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Edward Mottram ,  Matthew David Eaton

IPC: G06F30/327 ,  G06F111/04 ,  G06F111/20

Abstract: For a division of a dividend by a constant divider, a circuit architecture may calculate partial remainders. The circuit architecture may implement a tree structure to generate intermediate signals of partial remainders and combine adjacent intermediate signals to generate other partial remainders downstream. The circuit architecture may generate a quotient based on the partial remainders. The circuit architecture may also implement bit shifting and zero-padding on left side of the dividend to generate bit-level partial remainders. Furthermore, the circuit architecture may enable a fast round-to-zero division of signed integers by flipping the input bits of a negative integer and output bits of the corresponding quotient and performing only one increment operation, either before the division or after the division. In addition, the circuit architecture may also perform a division of a dividend in a carry-save form.