Static timing analysis methods for integrated circuit designs using a multi-CCC current source model
    1.
    发明授权
    Static timing analysis methods for integrated circuit designs using a multi-CCC current source model 有权
    使用多CCC电流源模型的集成电路设计的静态时序分析方法

    公开(公告)号:US08966421B1

    公开(公告)日:2015-02-24

    申请号:US14023450

    申请日:2013-09-10

    CPC classification number: G06F17/5081 G06F17/5036 G06F2217/84

    Abstract: In one embodiment of the invention, a multi-CCC current source model is disclosed to perform statistical timing analysis of an integrated circuit design. The multi-CCC current source model includes a voltage waveform transfer function, a voltage dependent current source, and an output capacitor. The voltage waveform transfer function receives an input voltage waveform and transforms it into an intermediate voltage waveform. The voltage dependent current source generates an output current in response to the intermediate voltage waveform. The output capacitor is coupled in parallel to the voltage dependent current source to generate an output voltage waveform for computation of a timing delay.

    Abstract translation: 在本发明的一个实施例中,公开了一种多CCC电流源模型来执行集成电路设计的统计时序分析。 多CCC电流源模型包括电压波形传递函数,电压相关电流源和输出电容器。 电压波形传递函数接收输入电压波形并将其转换为中间电压波形。 电压相关电流源响应于中间电压波形产生输出电流。 输出电容器并联到与电压相关的电流源,以产生用于计算定时延迟的输出电压波形。

    Generating an equivalent waveform model in static timing analysis
    3.
    发明授权
    Generating an equivalent waveform model in static timing analysis 有权
    在静态时序分析中生成等效波形模型

    公开(公告)号:US08726211B2

    公开(公告)日:2014-05-13

    申请号:US13632885

    申请日:2012-10-01

    CPC classification number: G06F17/5036 G06F2217/84

    Abstract: A method is provided for use during static timing analysis of an integrated circuit design to produce an equivalent waveform model, the method comprising: using an analog model of the inner component, to simulate an inner component to produce multiple analog simulation output characterization waveforms as a function of multiple input waveforms used to characterize the design cell; using the analog model of the inner component to simulate the inner component to produce an analog simulation output waveform as a function of the complex waveform; and producing the equivalent waveform model as a function of the multiple analog simulation output characterization waveforms and the analog simulation output waveform.

    Abstract translation: 提供了一种用于在集成电路设计的静态时序分析期间用于产生等效波形模型的方法,所述方法包括:使用内部组件的模拟模型来模拟内部组件以产生多个模拟仿真输出表征波形作为 用于表征设计单元的多个输入波形的功能; 使用内部组件的模拟模型来模拟内部组件,以产生作为复杂波形的函数的模拟仿真输出波形; 并产生等效波形模型作为多个模拟仿真输出特性波形和模拟仿真输出波形的函数。

    GENERATING AN EQUIVALENT WAVEFORM MODEL IN STATIC TIMING ANALYSIS
    4.
    发明申请
    GENERATING AN EQUIVALENT WAVEFORM MODEL IN STATIC TIMING ANALYSIS 有权
    在静态时序分析中产生等效波形模型

    公开(公告)号:US20140096099A1

    公开(公告)日:2014-04-03

    申请号:US13632885

    申请日:2012-10-01

    CPC classification number: G06F17/5036 G06F2217/84

    Abstract: A method is provided for use during static timing analysis of an integrated circuit design to produce an equivalent waveform model, the method comprising: using an analog model of the inner component, to simulate an inner component to produce multiple analog simulation output characterization waveforms as a function of multiple input waveforms used to characterize the design cell; using the analog model of the inner component to simulate the inner component to produce an analog simulation output waveform as a function of the complex waveform; and producing the equivalent waveform model as a function of the multiple analog simulation output characterization waveforms and the analog simulation output waveform.

    Abstract translation: 提供了一种用于在集成电路设计的静态时序分析期间用于产生等效波形模型的方法,所述方法包括:使用内部组件的模拟模型来模拟内部组件以产生多个模拟仿真输出表征波形作为 用于表征设计单元的多个输入波形的功能; 使用内部组件的模拟模型来模拟内部组件,以产生作为复杂波形的函数的模拟仿真输出波形; 并产生等效波形模型作为多个模拟仿真输出特性波形和模拟仿真输出波形的函数。

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