公开(公告)号：US11216606B1

公开(公告)日：2022-01-04

申请号：US16942801

申请日：2020-07-30

Applicant: Cadence Design Systems, Inc.

Inventor： Ophir Turbovich ,  Muhammad Zoabi ,  Yuval Shpak

IPC: G06F30/3308 ,  G06F119/02 ,  G06F117/04

Abstract: A computer implemented method for functional safety verification includes simulating SA0 and/or SA1 faults at a Q output port of each sequential element in a first representation of an electronic design, to determine whether any of the simulated faults is detectable by a safety mechanism, determining, based on one or more fault relation rules and based on a second gate-level representation of the electronic design, whether any of the faults is also detectable by the safety mechanism if occurred at one or more input ports of the respective sequential element or one or more input ports of a clockgate of the respective sequential element, and identifying a remainder of input ports and input ports of a clockgate of each of the sequential elements at which the faults are not determined to be detectable by the safety mechanism based on the one or a plurality of fault relation rules.