公开(公告)号：US10262088B1

公开(公告)日：2019-04-16

申请号：US15461205

申请日：2017-03-16

Applicant: Cadence Design Systems, Inc.

Inventor： Ophir Turbovich ,  Yosinori Watanabe

IPC: G06F17/50

Abstract: A method for converting real number modeling to cycle-driven simulation interface file is provided. The method includes verifying an input in a file that includes a real number modeling code, cleaning the real number modeling code in the file, converting the file to a cycle-driven simulation interface file, and verifying the cycle-driven simulation interface file. Converting the method includes building a definitions file storing a width of at least one real number in the circuit design, and selecting a real number modeling file from the circuit design. For the real number modeling file, the method includes parsing the real number modeling file, building a header file associated with the real number modeling file, and building a compilation file associated with the cycle-driven simulation interface file. A system and a non-transitory, computer readable medium to perform the above method are also provided.

公开(公告)号：US11748539B1

公开(公告)日：2023-09-05

申请号：US15718775

申请日：2017-09-28

Applicant: Cadence Design Systems, Inc.

Inventor： Ophir Turbovich ,  Yosinori Watanabe

IPC: G06F30/33

CPC classification number: G06F30/33

Abstract: A method and a system for converting a variable delay in real number modeling code to cycle-driven simulation interface event for digital/mixed signal emulation is provided. The method comprises identifying a variable delay of an analog signal in real number modeling code defining an analog circuit; determining a frequency and a maximum number of cycles for a series of discrete clock cycles, wherein the variable delay corresponds to one cycle in the series of discrete clock cycles; converting the variable delay into a plurality of cycle-driven discrete events based on the series of discrete clock cycles; and generating synthesizable code based on the plurality of cycle-driven discrete events for digital mixed signal emulation. A system and a non-transitory computer readable medium to perform the above method are also provided.

公开(公告)号：US10133836B1

公开(公告)日：2018-11-20

申请号：US15272003

申请日：2016-09-21

Applicant: Cadence Design Systems, Inc.

Inventor： Ophir Turbovich ,  Vasant Ramabadran

IPC: G06F17/50

Abstract: A method for on-the-fly determination of leakage power and temperature of an electronic circuit design is provided. The method includes calculating a dynamic power of the electronic circuit design. The method also includes calculating a total power consumption of the electronic circuit design. The method further includes averaging the total power consumption to obtain an average total power, determining a temperature of the electronic circuit design based on the average total power, and determining a leakage power of the electronic circuit design based on the temperature. A system and a non-transitory, computer-readable medium storing computer-readable instructions to perform the above method are also provided.

公开(公告)号：US10262095B1

公开(公告)日：2019-04-16

申请号：US15718788

申请日：2017-09-28

Applicant: Cadence Design Systems, Inc.

Inventor： Ophir Turbovich ,  Yosinori Watanabe

IPC: G06F17/50 ,  G06F8/41

Abstract: A method for converting real number modeling to a cycle-driven simulation interface file is provided. The method includes verifying an input in a file that includes a real number modeling code, requesting a user input parameter, converting the file to a cycle-driven simulation interface file based on the user input parameter, and verifying the cycle-driven simulation interface file. Converting the method includes building a definitions file storing a width of at least one real number in the circuit design, and selecting a real number modeling file from the circuit design. For the real number modeling file, the method includes parsing the real number modeling file, building a header file associated with the real number modeling file, and building a compilation file associated with the cycle-driven simulation interface file. A system and a computer readable medium to perform the above method are also provided.

公开(公告)号：US11216606B1

公开(公告)日：2022-01-04

申请号：US16942801

申请日：2020-07-30

Applicant: Cadence Design Systems, Inc.

Inventor： Ophir Turbovich ,  Muhammad Zoabi ,  Yuval Shpak

IPC: G06F30/3308 ,  G06F119/02 ,  G06F117/04

Abstract: A computer implemented method for functional safety verification includes simulating SA0 and/or SA1 faults at a Q output port of each sequential element in a first representation of an electronic design, to determine whether any of the simulated faults is detectable by a safety mechanism, determining, based on one or more fault relation rules and based on a second gate-level representation of the electronic design, whether any of the faults is also detectable by the safety mechanism if occurred at one or more input ports of the respective sequential element or one or more input ports of a clockgate of the respective sequential element, and identifying a remainder of input ports and input ports of a clockgate of each of the sequential elements at which the faults are not determined to be detectable by the safety mechanism based on the one or a plurality of fault relation rules.

公开(公告)号：US10133837B1

公开(公告)日：2018-11-20

申请号：US15405623

申请日：2017-01-13

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Ophir Turbovich ,  Yosinori Watanabe ,  Michael Young ,  Sean Dart

IPC: G06F17/50 ,  G06F7/483

Abstract: A method for converting a real number modeling to a synthesizable register-transfer level emulation in digital mixed signal environments is provided. The method includes verifying an input in a file including a real number modeling code and cleaning the real number modeling code in the file. The method also includes separating a clean register-transfer level code from the real number modeling code, converting the file to a cycle-driven simulation interface file, and verifying the cycle-driven simulation interface file. The method further includes converting the cycle-driven simulation interface file into a register-transfer level file suitable to perform a circuit emulation in digital mixed signal environments, and verifying that the register-transfer level file is ready to perform circuit emulation in the digital mixed signal environments. A system and a non-transitory, computer readable medium storing commands to perform the above method are also provided.