公开(公告)号：US09760667B1

公开(公告)日：2017-09-12

申请号：US14320444

申请日：2014-06-30

Applicant: Cadence Design Systems, Inc.

Inventor： Oleg Levitsky ,  Paul W. Kollaritsch

IPC: G06F17/50

CPC classification number: G06F17/5059

Abstract: Methods and systems for implementing prototyping and floorplanning for electronic circuit designs are disclosed. The method identifies or generates a representation of a design, modifies or updates the representation by moving a circuit component in the representation. The representation may be characterized in the pre-placement or post-placement stage to determine or identify distance constraints constraining object pairs in the representation. The method performs a timing and/or congestion analysis with distance-based timing information having a spatial dimension rather than timing information having a temporal dimension for the representation of the electronic design. The timing and/or congestion analysis is performed during the circuit component is being moved or shortly after the circuit component has been moved. The results of the timing and/or congestion analysis are provided in an interactive manner or in a batch mode.

公开(公告)号：US08769455B1

公开(公告)日：2014-07-01

申请号：US13719058

申请日：2012-12-18

Applicant: Cadence Design Systems, Inc.

Inventor： Sushobhit Singh ,  Amit Kumar ,  Oleg Levitsky

IPC: G06F17/50 ,  G06F9/455

CPC classification number: G06F17/5045 ,  G06F17/505 ,  G06F2217/84

Abstract: Various embodiments use connectivity information or model(s), design attribute(s), and system intelligence layer(s) to make lower blocks at lower levels aware of changes made in other blocks at same or different levels to implement the design at different levels synchronously. Budgeting is performed for the design to distribute budgets to respective blocks in the design. The various budgets may be borrowed from one or more blocks and lent to a block in order for this block to meet closure requirements such that a total number of iterations of the reassembly process, which integrates lower level blocks into top level design, may be reduced or completely eliminated. The design attribute(s) or the connectivity model(s) or information is updated upon the identification of changes to provide the latest information or data for properly closing a design.

Abstract translation: 各种实施例使用连通性信息或模型，设计属性和系统智能层，以使较低级别的较低块知道在相同或不同级别的其他块中进行的改变，以在不同级别实现设计 同步地 执行预算设计以将预算分配到设计中的各个块。 可以从一个或多个块借用各种预算并借出块，以便该块满足关闭要求，使得可以减少将较低级别块集成到顶级设计中的重组过程的迭代次数 或完全消除。 设计属性或连接模型或信息将在识别更改时更新，以提供正确关闭设计的最新信息或数据。

公开(公告)号：US09165098B1

公开(公告)日：2015-10-20

申请号：US13716131

申请日：2012-12-15

Applicant: Cadence Design Systems, Inc.

Inventor： Vivek Bhardwaj ,  Oleg Levitsky ,  Dinesh Gupta

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5031 ,  G06F17/505 ,  G06F17/5068 ,  G06F2217/62 ,  G06F2217/84

Abstract: In one embodiment of the invention, a method includes partitioning an integrated circuit design into a hierarchy of a top level and a plurality of partitions, wherein the top level includes a top level netlist and each partition includes a partition netlist; receiving data path timing budgets and clock path timing budgets for each of the plurality of partitions of the integrated circuit design; and generating a timing budget model of each partition in response to the respective data path timing budgets and clock path timing budgets, wherein each timing budget model includes an intra-partition clock timing constraint for each respective partition for independent implementation of the top level.

Abstract translation: 在本发明的一个实施例中，一种方法包括将集成电路设计划分成顶层和多个分区的层级，其中顶层包括顶级网表，每个分区包括分区网表; 接收所述集成电路设计的所述多个分区中的每一个的数据路径定时预算和时钟路径时序预算; 以及响应于相应的数据路径定时预算和时钟路径定时预算，生成每个分区的定时预算模型，其中每个定时预算模型包括用于每个相应分区的分区内时钟定时约束，用于独立实现顶层。

公开(公告)号：US09152742B1

公开(公告)日：2015-10-06

申请号：US14051039

申请日：2013-10-10

Applicant: Cadence Design Systems, Inc.

Inventor： Dinesh Gupta ,  Oleg Levitsky

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/50 ,  G06F17/505 ,  G06F2217/84

Abstract: In one embodiment, a method of designing an integrated circuit is disclosed, including receiving a first partition block for a top level of a hierarchical design of an integrated circuit; analyzing each pin of the first partition block for an attribute associated with the pin indicating a timing exception; and if a timing exception other than false path is indicated then generating an internal timing pin in a first timing graph model of the first partition block for each timing exception, and adding a timing arc and a dummy arc coupled to the internal timing pin in the first timing graph model of the first partition block. The internal timing pin adds a timing exception constraint for each timing exception. Timing of the top level may then be analyzed with the first timing graph model to determine if timing constraints, including the added timing exception constraints, are met.

Abstract translation: 在一个实施例中，公开了一种设计集成电路的方法，包括接收用于集成电路的分层设计的顶层的第一分区块; 分析第一分区块的每个引脚以获得与引脚相关联的指示定时异常的属性; 并且如果指示除了假路径之外的定时异常，则针对每个定时异常在第一分区块的第一定时图模型中生成内部定时引脚，并且将定时弧和虚拟电弧相加到内部定时引脚 第一分区块的第一时序图模型。 内部定时引脚为每个定时异常添加时序异常约束。 然后可以用第一时序图模型来分析顶级的定时，以确定是否满足包括添加的时序异常约束的时序约束。

公开(公告)号：US09053270B1

公开(公告)日：2015-06-09

申请号：US14298848

申请日：2014-06-06

Applicant: Cadence Design Systems, Inc.

Inventor： Sushobhit Singh ,  Amit Kumar ,  Oleg Levitsky

IPC: G06F17/50 ,  G06F9/455

CPC classification number: G06F17/5045 ,  G06F17/505 ,  G06F2217/84

Abstract: Various embodiments use connectivity information or model(s), design attribute(s), and system intelligence layer(s) to make lower blocks at lower levels aware of changes made in other blocks at same or different levels to implement the design at different levels synchronously. Budgeting is performed for the design to distribute budgets to respective blocks in the design. The various budgets may be borrowed from one or more blocks and lent to a block in order for this block to meet closure requirements such that a total number of iterations of the reassembly process, which integrates lower level blocks into top level design, may be reduced or completely eliminated. The design attribute(s) or the connectivity model(s) or information is updated upon the identification of changes to provide the latest information or data for properly closing a design.

Abstract translation: 各种实施例使用连通性信息或模型，设计属性和系统智能层，以使较低级别的较低块知道在相同或不同级别的其他块中进行的改变，以在不同级别实现设计 同步地 执行预算设计以将预算分配到设计中的各个块。 可以从一个或多个块借用各种预算并借出块，以便该块满足关闭要求，使得可以减少将较低级别块集成到顶级设计中的重组过程的迭代次数 或完全消除。 设计属性或连接模型或信息将在识别更改时更新，以提供正确关闭设计的最新信息或数据。