公开(公告)号：US09026960B1

公开(公告)日：2015-05-05

申请号：US13672606

申请日：2012-11-08

Applicant: Cadence Design Systems, Inc.

Inventor： Chayan Majumder ,  Pawan Fangaria

IPC: G06F17/50

CPC classification number: G06F17/50 ,  G06F17/5072 ,  G06F2217/12 ,  Y02P90/265

Abstract: The present invention is directed towards designing integrated circuit and provides systems and methods for lithography-aware floorplanning. According to one embodiment of the invention, a method for circuit floorplanning is provided. The method comprises generating a floorplan through a floorplanner, performing a lithography-analysis within the floorplanner on at least a portion of the floorplan, and generating one or more violations that result from the lithography-analysis. Some embodiment, in addition to viewing a floorplan, further comprise of modifying the floorplan. Furthermore, some embodiments provide a method that further comprises fixing the violations that result from the lithography analysis.

Abstract translation: 本发明旨在设计集成电路并提供用于光刻感知布局规划的系统和方法。 根据本发明的一个实施例，提供了一种用于电路布局规划的方法。 该方法包括通过平面图生成平面布置图，在平面布置图中对平面图的至少一部分进行光刻分析，以及产生由光刻分析产生的一个或多个违规。 除了观看平面图之外，一些实施例还包括修改平面图。 此外，一些实施例提供了一种进一步包括固定由光刻分析产生的违规的方法。