公开(公告)号：US10467371B1

公开(公告)日：2019-11-05

申请号：US15493579

申请日：2017-04-21

Applicant: Cadence Design Systems, Inc.

Inventor： Chayan Majumder ,  Arnold Jean Marie Gustave Ginetti

IPC: G06F17/50

Abstract: The present disclosure relates to a computer-implemented method for use in an electronic circuit design. Embodiments may include receiving, using at least one processor, the electronic circuit design and displaying, via a graphical user interface, a first device associated with the electronic circuit design. Embodiments may further include displaying, via the graphical user interface, a second device associated with the electronic circuit design. Embodiments may also include displaying, via the graphical user interface, inter-device connectivity between the first device and the second device and displaying intra-device connectivity between at least one of the first device and the second device, wherein the inter-device connectivity and the intra-device connectivity are visibly distinct.

公开(公告)号：US10133841B1

公开(公告)日：2018-11-20

申请号：US15282792

申请日：2016-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Chayan Majumder ,  Arnold Ginetti ,  Chandra Prakash Manglani ,  Amit Kumar

IPC: G06F17/50

Abstract: Disclosed are techniques for implementing three-dimensional or multi-layer integrated circuit designs. These techniques identify an electronic design and a plurality of inputs for implementing connectivity for the electronic design. Net distribution results may be generated at least by performing one or more net distribution analyzes. A bump in a bump array may then be assigned to a net that connects a first layer and a second layer in the electronic design based in part or in whole upon the net distribution analysis results.

公开(公告)号：US09026960B1

公开(公告)日：2015-05-05

申请号：US13672606

申请日：2012-11-08

Applicant: Cadence Design Systems, Inc.

Inventor： Chayan Majumder ,  Pawan Fangaria

IPC: G06F17/50

CPC classification number: G06F17/50 ,  G06F17/5072 ,  G06F2217/12 ,  Y02P90/265

Abstract: The present invention is directed towards designing integrated circuit and provides systems and methods for lithography-aware floorplanning. According to one embodiment of the invention, a method for circuit floorplanning is provided. The method comprises generating a floorplan through a floorplanner, performing a lithography-analysis within the floorplanner on at least a portion of the floorplan, and generating one or more violations that result from the lithography-analysis. Some embodiment, in addition to viewing a floorplan, further comprise of modifying the floorplan. Furthermore, some embodiments provide a method that further comprises fixing the violations that result from the lithography analysis.

Abstract translation: 本发明旨在设计集成电路并提供用于光刻感知布局规划的系统和方法。 根据本发明的一个实施例，提供了一种用于电路布局规划的方法。 该方法包括通过平面图生成平面布置图，在平面布置图中对平面图的至少一部分进行光刻分析，以及产生由光刻分析产生的一个或多个违规。 除了观看平面图之外，一些实施例还包括修改平面图。 此外，一些实施例提供了一种进一步包括固定由光刻分析产生的违规的方法。

公开(公告)号：US09672308B1

公开(公告)日：2017-06-06

申请号：US14645360

申请日：2015-03-11

Applicant: Cadence Design Systems, Inc.

Inventor： Chayan Majumder

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/5045 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/06

Abstract: Disclosed are mechanisms for implementing three-dimensional operations for electronic circuit designs. These mechanisms identify a cross-layer layout portion by identifying a first electronic design as an editable layout portion and a second electronic design as a selectable and non-editable layout portion in a single window, determine a ruler by identifying or generating the ruler for a three-dimensional operation across the first electronic design and the second electronic design on different layers, identify one or more starting targets and one or more end targets within an aperture at least by determining the one or more starting targets and one or more end targets based in part or in whole upon a location of the aperture and the one or more rulers, and perform the three-dimensional operation at least by manipulating a plurality of shapes in the cross-layer layout portion based in part or in whole upon the one or more rulers.