公开(公告)号：US11947887B1

公开(公告)日：2024-04-02

申请号：US17953618

申请日：2022-09-27

Applicant: Cadence Design Systems, Inc.

Inventor： Krishna Chakravadhanula ,  Brian Foutz ,  Prateek Kumar Rai ,  Sarthak Singhal ,  Christos Papameletis ,  Vivek Chickermane

IPC: G06F30/333 ,  G06F30/327 ,  G01R31/3185

CPC classification number: G06F30/333 ,  G06F30/327 ,  G01R31/318583

Abstract: A system includes a memory that stores instructions and receives a circuit netlist, and includes a processing unit that accesses the memory and executes the instructions. The instructions include an EDA application that includes a test-point flop allocation module that is configured to evaluate the circuit netlist to determine compatibility of the test-point nodes in the circuit netlist. The test-point flop allocation module can further allocate each of the test-point flops to a test-point sharing group comprising a plurality of compatible test-point nodes. The EDA application also includes a circuit layout module configured to generate a circuit layout associated with the circuit design, the circuit layout comprising the functional logic and scan-chains comprising the test-point flops allocated to the test-point sharing groups in response to the circuit netlist. The circuit layout is employable to fabricate an integrated circuit (IC) chip.