公开(公告)号：US11947887B1

公开(公告)日：2024-04-02

申请号：US17953618

申请日：2022-09-27

申请人： Cadence Design Systems, Inc.

发明人： Krishna Chakravadhanula ,  Brian Foutz ,  Prateek Kumar Rai ,  Sarthak Singhal ,  Christos Papameletis ,  Vivek Chickermane

IPC分类号： G06F30/333 ,  G06F30/327 ,  G01R31/3185

CPC分类号： G06F30/333 ,  G06F30/327 ,  G01R31/318583

摘要： A system includes a memory that stores instructions and receives a circuit netlist, and includes a processing unit that accesses the memory and executes the instructions. The instructions include an EDA application that includes a test-point flop allocation module that is configured to evaluate the circuit netlist to determine compatibility of the test-point nodes in the circuit netlist. The test-point flop allocation module can further allocate each of the test-point flops to a test-point sharing group comprising a plurality of compatible test-point nodes. The EDA application also includes a circuit layout module configured to generate a circuit layout associated with the circuit design, the circuit layout comprising the functional logic and scan-chains comprising the test-point flops allocated to the test-point sharing groups in response to the circuit netlist. The circuit layout is employable to fabricate an integrated circuit (IC) chip.

公开(公告)号：US12007440B1

公开(公告)日：2024-06-11

申请号：US17847421

申请日：2022-06-23

申请人： Cadence Design Systems, Inc.

发明人： Puneet Arora ,  Subhasish Mukherjee ,  Sarthak Singhal ,  Christos Papameletis ,  Brian Foutz ,  Krishna V Chakravadhanula ,  Ankit Bandejia ,  Norman Card

IPC分类号： G01R31/3185 ,  G01R31/317 ,  G06F11/267 ,  G06F30/333 ,  G11C29/32

CPC分类号： G01R31/318536 ,  G01R31/318547 ,  G01R31/31704 ,  G01R31/3185 ,  G01R31/318558 ,  G01R31/318563 ,  G01R31/318583 ,  G06F11/267 ,  G06F30/333 ,  G11C29/32 ,  G11C2029/3202

摘要： This disclosure relates scan chain stitching. In one example, scan chain elements from a scan chain element space can be received for a scan chain partition. The scan chain elements can be grouped based on scan chain element grouping criteria to form scan chain groups. Scan chain data identifying a number of scan chains for the scan chain partition can be received. The scan chains can be scan chain balanced across the scan chain groups to assign each scan chain to one of the scan chain groups. The scan chain elements associated with each scan chain of the scan chains can be scan chain element balanced. Scan chain elements for each associated scan chain can be connected to form a scan chain data test path during a generation of scan chain circuitry in response to the scan chain element balancing.