公开(公告)号：US10185795B1

公开(公告)日：2019-01-22

申请号：US15290356

申请日：2016-10-11

Applicant: Cadence Design Systems, Inc.

Inventor： Igor Keller ,  Praveen Ghanta ,  Arun Kumar Mishra

IPC: G06F17/50

Abstract: Electronic design automation systems, methods, and media are presented for characterizing on-chip variation of circuit elements in a circuit design using statistical values including skew, and for performing statistical static timing analysis using these statistical values. One embodiment models delay characteristics under certain operating conditions for circuit elements with asymmetric (e.g., non-Gaussian) probability density functions using normalized skewness. The modeled delay can then be used to perform various timing analysis operations.

公开(公告)号：US10430536B1

公开(公告)日：2019-10-01

申请号：US15721148

申请日：2017-09-29

Applicant: Cadence Design Systems, Inc.

Inventor： Igor Keller ,  Praveen Ghanta ,  Mikhail Chetin

IPC: G06F17/50

Abstract: An approach is described for yield calculation using statistical timing data that accounts for path and stage delay correlation. Embodiments of the present invention provide an improved approach for yield calculation using statistical timing data that accounts for path and stage delay correlation. According to some embodiments, the approach includes receiving statistical timing analysis data, identifying paths for performing timing analysis, performing timing analysis where common segments of different paths are analyzed using shared data and where subsequent stages are transformed to provide an expected correlation between stages, and generating yield probability results based on at least the results of calculating timing analysis.

公开(公告)号：US10275554B1

公开(公告)日：2019-04-30

申请号：US15652130

申请日：2017-07-17

Applicant: Cadence Design Systems, Inc.

Inventor： Mikhail Chetin ,  Igor Keller ,  Praveen Ghanta

IPC: G06F17/50 ,  G06F17/15 ,  G06F16/901

Abstract: A method as provided includes retrieving a correlation value from a correlation table and a coskewness value from a coskewness table. The correlation value includes a correlation between a delay distribution and a slew rate distribution, and is associated with both: an input slew rate and an output load, in a logic stage in an integrated circuit design, and the coskewness value is a coskewness between the delay distribution and the slew rate distribution. The method includes determining a partial derivative of a delay function relative to the input slew rate, determining a delay distribution for a signal through a plurality of logic stages using the correlation value, the coskewness value, and the partial derivative of the delay function relative to the input slew rate. The method also includes verifying that a statistical value of the delay distribution satisfies a desired performance value for an integrated circuit.

公开(公告)号：US10073934B1

公开(公告)日：2018-09-11

申请号：US15290362

申请日：2016-10-11

Applicant: Cadence Design Systems, Inc.

Inventor： Igor Keller ,  Praveen Ghanta ,  Arun Kumar Mishra

IPC: G06F17/50

CPC classification number: G06F17/5031 ,  G06F2217/10

Abstract: Electronic design automation systems, methods, and media are presented for characterizing on-chip variation of circuit elements in a circuit design using statistical values including skew, and for performing statistical static timing analysis using these statistical values. One embodiment models delay characteristics under certain operating conditions for circuit elements with asymmetric (e.g., non-Gaussian) probability density functions using normalized skewness. This information is then accessed in other embodiments, and scaled to generate scaled timing values describing the statistical timing characteristics of a circuit element or block estimated from the skew-based values. These values may then be used for further timing analysis.