公开(公告)号：US09710593B1

公开(公告)日：2017-07-18

申请号：US14883482

申请日：2015-10-14

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Igor Keller ,  Mikhail Chetin ,  Xiaojun Sun

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5031

Abstract: Disclosed are techniques for enhancing timing analyses with reduced timing libraries for electronic designs. These techniques determine dominance relations for multiple timing models for timing analyses and generate a dominance adjacency data structure based at least in part upon the dominance relations. The dominance adjacency data structure may be stored at a first location of a non-transitory computer accessible storage medium. The plurality of timing models may be reduced into a reduced set of timing models at least by providing the dominance adjacency data structure as an input to a transformation and further by transforming the dominance adjacency data structure with the transformation into the reduced set of timing models that are used in timing analyses for an electronic design or a portion thereof.

公开(公告)号：US10430536B1

公开(公告)日：2019-10-01

申请号：US15721148

申请日：2017-09-29

Applicant: Cadence Design Systems, Inc.

Inventor： Igor Keller ,  Praveen Ghanta ,  Mikhail Chetin

IPC: G06F17/50

Abstract: An approach is described for yield calculation using statistical timing data that accounts for path and stage delay correlation. Embodiments of the present invention provide an improved approach for yield calculation using statistical timing data that accounts for path and stage delay correlation. According to some embodiments, the approach includes receiving statistical timing analysis data, identifying paths for performing timing analysis, performing timing analysis where common segments of different paths are analyzed using shared data and where subsequent stages are transformed to provide an expected correlation between stages, and generating yield probability results based on at least the results of calculating timing analysis.

公开(公告)号：US10275554B1

公开(公告)日：2019-04-30

申请号：US15652130

申请日：2017-07-17

Applicant: Cadence Design Systems, Inc.

Inventor： Mikhail Chetin ,  Igor Keller ,  Praveen Ghanta

IPC: G06F17/50 ,  G06F17/15 ,  G06F16/901

Abstract: A method as provided includes retrieving a correlation value from a correlation table and a coskewness value from a coskewness table. The correlation value includes a correlation between a delay distribution and a slew rate distribution, and is associated with both: an input slew rate and an output load, in a logic stage in an integrated circuit design, and the coskewness value is a coskewness between the delay distribution and the slew rate distribution. The method includes determining a partial derivative of a delay function relative to the input slew rate, determining a delay distribution for a signal through a plurality of logic stages using the correlation value, the coskewness value, and the partial derivative of the delay function relative to the input slew rate. The method also includes verifying that a statistical value of the delay distribution satisfies a desired performance value for an integrated circuit.