公开(公告)号：US11620548B1

公开(公告)日：2023-04-04

申请号：US16898702

申请日：2020-06-11

Applicant: Cadence Design Systems, Inc.

Inventor： Sai Bhushan ,  Elias Lee Fallon ,  Chirag Ahuja

IPC: G06F30/3308 ,  G06F30/27 ,  G06N5/04 ,  G06N5/00 ,  G06N20/20

Abstract: The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design having an original schematic associated therewith and extracting one or more features for each net from the schematic. Embodiments may include storing one or more resistance or capacitance values for each net and applying the one or more resistance or capacitance values as labels for a machine learning model. Embodiments may also include training the machine learning model using one or more actual values to generate a trained model. Embodiments may further include receiving the trained model to predict parasitics for a stitching engine and generating a stitched schematic.

公开(公告)号：US10997351B1

公开(公告)日：2021-05-04

申请号：US16992205

申请日：2020-08-13

Applicant: Cadence Design Systems, Inc.

Inventor： Sheng Qian ,  Sai Bhushan ,  Monica Goel

IPC: G06F30/392 ,  G06F30/3308

Abstract: Embodiments included herein are directed towards method for electronic design. Embodiments may include receiving, using at least one processor, a placed layout and one or more electronic design simulation datasets including current information associated with at least one pin. Embodiments may further include estimating a width to support the current information associated with the at least one pin and updating a pin size associated with the at least one pin based upon, at least in part, the estimated width. Embodiments may also include identifying at least one pin that is above a predetermined threshold and splitting the at least one pin that is above the predetermined threshold into a plurality of pins. Embodiments may further include generating one or more width-spacing-pattern tracks for one or more internal nets based upon, at least in part, the updated pin size.

公开(公告)号：US11829852B1

公开(公告)日：2023-11-28

申请号：US17007023

申请日：2020-08-31

Applicant: Cadence Design Systems, Inc.

Inventor： Sai Bhushan ,  Chirag Ahuja

IPC: G06N20/00 ,  H01L23/00 ,  G06F30/33 ,  G06F18/214

CPC classification number: G06N20/00 ,  G06F18/214 ,  G06F30/33 ,  H01L24/42 ,  H01L2924/14

Abstract: The present disclosure relates to a computer-implemented method for automatically determining pin placement associated with an electronic design. Embodiments may include receiving, using at least one processor, at least one layout associated with the electronic design and separating the at least one layout into one or more grids. Embodiments may also include extracting one or more connectivity features from the one or more grids, wherein the one or more connectivity features include instance-pin and pin information. Embodiments may also include training a machine learning model, based upon, at least in part, the one or more connectivity features and receiving the machine learning model and a test layout at a predictor engine. Embodiments may further include providing a user with a pin placement recommendation based upon, at least in part, the machine learning model and the test layout.