公开(公告)号：US10275555B1

公开(公告)日：2019-04-30

申请号：US15280839

申请日：2016-09-29

Applicant: Cadence Design Systems, Inc.

Inventor： Wangyang Zhang ,  Shikha Sharma ,  Hongzhou Liu

IPC: G06F9/455 ,  G06F17/50

Abstract: Method for estimating a yield of a post-layout circuit design is provided. In one aspect, a method includes obtaining a first pre-layout parameter and a second pre-layout parameter from pre-layout simulation samples of a circuit. The method also modeling a prior distribution of a first post-layout parameter and a second post-layout parameter based on the first pre-layout parameter, the second pre-layout parameter, a first hyper-parameter, and second hyper-parameter. The method further includes calculating the first hyper-parameter and the second hyper-parameter using a cross-validation, obtaining the first post-layout parameter and the second post-layout parameter based on the first hyper-parameter and the second hyper-parameter and estimating the yield of the circuit design using a non-normal distribution parameterized by the obtained first post-layout parameter and second post-layout parameter.