公开(公告)号：US12045730B1

公开(公告)日：2024-07-23

申请号：US16238274

申请日：2019-01-02

Applicant: Cadence Design Systems, Inc.

Inventor： Elias Lee Fallon ,  David Allan White ,  Regis R Colwell ,  Hongzhou Liu ,  Hui Xu ,  Wangyang Zhang ,  Shang Li ,  Hua Luo

IPC: G06N3/126 ,  G06F30/392

CPC classification number: G06N3/126 ,  G06F30/392

Abstract: The present disclosure relates to a computer-implemented method for genetic placement of analog and mix-signal circuit components. Embodiments may include receiving an unplaced layout associated with an electronic circuit design and grouping requirements. Embodiments may also include identifying one or more instances that need to be placed in the unplaced layout and areas of the unplaced layout configured to receive the instances. Embodiments may further include analyzing one or more instances that need to be placed in the unplaced layout and the areas of the unplaced layout configured to receive the instances, wherein analyzing is based upon a row-based data structure. Embodiments may also include determining a location and an orientation for each of the one or more instances based upon the genetic algorithm and generating a placed layout based upon the determined location and orientation for each of the instances.

公开(公告)号：US09805158B1

公开(公告)日：2017-10-31

申请号：US14942956

申请日：2015-11-16

Applicant: Cadence Design Systems, Inc.

Inventor： Hongzhou Liu ,  Stephan Weber ,  Wangyang Zhang

IPC: G06F17/00 ,  G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5009

Abstract: A system, method, and computer program product for efficiently finding the best Monte Carlo simulation samples for use as design corners for all design specifications to substitute for a full circuit design verification. Embodiments calculate a corner target value matching an input variation level by modeling the circuit performance with verified accuracy, estimate the corner based on a response surface model such that the corner has the highest probability density (or extrapolation from the worst sample if the model is inaccurate), and verify and/or adjust the corner by performing a small number of additional simulations. Embodiments also estimate the probability that a design already meets the design specifications at a specified variation level. Composite multimodal and non-Gaussian probability distribution functions enhance model accuracy. The extracted design corners may be of particular utility during circuit design iterations. A potential twenty-fold reduction in overall design specification verification time may be achieved.

公开(公告)号：US08954908B1

公开(公告)日：2015-02-10

申请号：US13939117

申请日：2013-07-10

Applicant: Cadence Design Systems, Inc.

Inventor： Hongzhou Liu ,  Jushan Xie ,  Michael Tian ,  An-Chang Deng

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F2217/10

Abstract: A system, method, and computer program product for automatically approximating conventional Monte Carlo statistical device model evaluation for circuit simulation with drastic speed improvements, while preserving significant accuracy. Embodiments enable quick inspection of the effects of process mismatch variations on single devices and even large circuits compared to standard computationally prohibitive Monte Carlo analysis. Statistical device model variation is calculated as if all such variation is due to changes in threshold voltage, even though other physical phenomena are known to contribute. Threshold voltage variation is modeled as a function of statistical variation, device size, and working bias condition. Circuit simulation is faster when the full internal device model parameter set is not rebuilt for every Monte Carlo analysis iteration. Embodiments are compatible with both conventional SPICE and newer Fast SPICE simulations. Circuit designers may capture design sensitivity to manufacture process changes more easily with simplified statistical models.

Abstract translation: 一种系统，方法和计算机程序产品，用于自动逼近传统的蒙特卡罗统计设备模型评估电路仿真，同时保持显着的精度。 与标准的计算禁止蒙特卡洛分析相比，实施例能够快速检查单个装置甚至大电路上的工艺不匹配变化的影响。 计算统计设备模型的变化，好像所有这些变化都是由于阈值电压的变化，即使其他物理现象已知有贡献。 阈值电压变化被建模为统计变化，器件尺寸和工作偏置条件的函数。 对于每个蒙特卡罗分析迭代，当不重建完整的内部设备模型参数集时，电路仿真更快。 实施例与传统的SPICE和更新的Fast SPICE仿真兼容。 电路设计人员可以通过简化的统计模型来捕获设计灵敏度，更容易地制造过程变化。

公开(公告)号：US11790147B1

公开(公告)日：2023-10-17

申请号：US17532087

申请日：2021-11-22

Applicant: Cadence Design Systems, Inc.

Inventor： Hongzhou Liu ,  Rahaprian Premavathi Mudiarasan ,  Sandipan Ghosh ,  Hui Xu ,  Chris (Shyh-Chang) Lin ,  Joshua Baudhuin ,  Ron Pyke ,  Juno Lin ,  Allen You ,  Yu Liu ,  Jiulong Zhang ,  Thomas Richards

IPC: G06F30/3953 ,  G06F30/31 ,  G06F30/398 ,  G06F30/3947 ,  G06F30/394

CPC classification number: G06F30/3953 ,  G06F30/31 ,  G06F30/394 ,  G06F30/398 ,  G06F30/3947

Abstract: Embodiments include herein are directed towards a method for electronic circuit design. Embodiments may include receiving, using a processor, an electronic design library including a plurality of design rules. Embodiments may include generating a routing graph, based upon, at least in part, the plurality of design rules, wherein the routing graph is a virtual representation of all of the available routing space for all routing layers associated with an electronic design. Embodiments may further include dynamically updating the routing graph at a graphical user interface, based upon, at least in part, a creation of a routing segment or a via at the graphical user interface.

公开(公告)号：US11562110B1

公开(公告)日：2023-01-24

申请号：US16587394

申请日：2019-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Wangyang Zhang ,  Hongzhou Liu ,  Hua Luo ,  Elias Lee Fallon

IPC: G06F17/00 ,  G06F30/20 ,  G06N20/00 ,  G06N7/00

Abstract: A system, method, and computer program product for predicting mismatch contribution in an electronic environment. Embodiments may include modeling, using a processor, a discrete output mismatch contribution problem using sparse logistic regression to generate a mismatch contribution model and applying a cross-validation approach to increase a complexity of the mismatch contribution model. Embodiments may further include computing one or more mismatch contribution values from the mismatch contribution model and defining at least one sizing constraint or determining a worst case result associated with a sampling process based upon, at least in part, the one or more mismatch contribution values.

公开(公告)号：US10853550B1

公开(公告)日：2020-12-01

申请号：US16027231

申请日：2018-07-03

Applicant: Cadence Design Systems, Inc.

Inventor： Wangyang Zhang ,  Hongzhou Liu ,  Richard J. O'Donovan ,  Michael Tian

IPC: G06F30/367 ,  G06F17/50 ,  G06F111/10 ,  G06F119/18

Abstract: A method for performing multiple simulations for a circuit using a first plurality of samples is provided. The method includes obtaining a model of the circuit based on a result of the simulations, determining a failure rate and a confidence interval of the failure rate for the circuit with the performance model. The method includes determining an importance distribution based on the failure rate for the first plurality of samples, wherein the importance distribution is indicative of a probability that a sample value for the circuit will fail the simulation, selecting a second plurality of samples based on the importance distribution, performing a second set of simulations using the second plurality of samples to reduce the confidence interval of the failure rate. When the confidence interval is larger than a value, obtaining an updated performance model and performing new Monte Carlo simulations with new samples.

公开(公告)号：US10262092B1

公开(公告)日：2019-04-16

申请号：US15589762

申请日：2017-05-08

Applicant: Cadence Design Systems, Inc.

Inventor： Wangyang Zhang ,  Hongzhou Liu ,  Catherine Bunting

IPC: G06F17/50

Abstract: A method for determining mismatch variation of circuit components in a circuit is provided. The method includes determining a mismatch contribution for a specification of an integrated circuit design and displaying a list of components in the circuit design sorted according to the mismatch contribution. The method also includes displaying an adjustable scale for a size of the component, modifying the circuit design according to with the size of the component adjusted according to a user input to the adjustable scale, determining an adjusted mismatch contribution of the component, and displaying in the list of components a modified value of the mismatch contribution, and a modified value of an overall standard deviation for the specification in the circuit design.

公开(公告)号：US10084476B1

公开(公告)日：2018-09-25

申请号：US15847604

申请日：2017-12-19

Applicant: Cadence Design Systems, Inc.

Inventor： Jianzhou Zhao ,  Daniel de Fonseca Munford Argollo ,  Vuk Borich ,  Hongzhou Liu

IPC: H03M7/30

CPC classification number: H03M7/30 ,  H03M7/3084

Abstract: A method including separating multiple signal waveforms into multiple blocks forming a sequence is provided. Each of the blocks includes at least a portion of each of the multiple signal waveforms. The method includes identifying a shared time portion and a shared signal portion for the signal waveforms within a first block from the multiple blocks and selecting a format for the first block based on a block size of the first block and a block read time of the first block. The method also includes compressing data in the first block based on the shared time portion, the shared signal portion, a preceding block and a subsequent block in the sequence, and storing the first block in a memory based on the format selected for the first block.

公开(公告)号：US08954910B1

公开(公告)日：2015-02-10

申请号：US14166119

申请日：2014-01-28

Applicant: Cadence Design Systems, Inc.

Inventor： Hongzhou Liu ,  Wangyang Zhang

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5009 ,  G06F2217/10 ,  G06F2217/16

Abstract: A system, method, and computer program product for computing device mismatch variation contributions to circuit performance variation. Embodiments estimate which individual devices in a simulated circuit design have the largest impact on circuit performance, while requiring far fewer simulations than traditional multivariate linear regressions. When the samples exceed the mismatch parameters, a linear model is solved by least squares. Otherwise, a linear model is solved by orthogonal matching pursuit (OMP), and if that solution is too inaccurate then a new mixed method builds a better linear model. If the linear solution is too inaccurate, a full linear and quadratic model is made using OMP to select the most important variables, and the full model is fitted using OMP with selected cross terms. The embodiments summarize the output variance in each device, and rank the mismatch contributions based on the summarized contributions.

Abstract translation: 一种用于计算设备失配变化对电路性能变化的贡献的系统，方法和计算机程序产品。 实施例估计了模拟电路设计中的哪些单独设备对电路性能的影响最大，同时比传统的多元线性回归要少得多的仿真。 当样本超过失配参数时，通过最小二乘求解线性模型。 否则，通过正交匹配追求（OMP）解决线性模型，如果该解决方案太不准确，则新的混合方法建立更好的线性模型。 如果线性解决方案太不准确，则使用OMP来选择最重要的变量来完成线性和二次模型，并且使用具有所选交叉项的OMP拟合完整模型。 这些实施例总结了每个设备中的输出差异，并且基于总结的贡献对不匹配贡献进行排序。

公开(公告)号：US08813009B1

公开(公告)日：2014-08-19

申请号：US13830696

申请日：2013-03-14

Applicant: Cadence Design Systems, Inc.

Inventor： Hongzhou Liu ,  Wangyang Zhang

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F17/5036 ,  G06F2217/10 ,  G06F2217/16

Abstract: A system, method, and computer program product for computing device mismatch variation contributions to circuit performance variation. Embodiments estimate which individual devices in a simulated circuit design have the largest impact on circuit performance, while requiring far fewer simulations than traditional multivariate linear regressions. An ordered metric allocates output variance contributions for each input mismatch parameter in a linear model. The embodiments summarize the output variance in each device, and rank the mismatch contributions based on the summarized contributions. Additional sensitivity analysis can derive a final accurate linear contribution. Embodiments can reduce required simulations by a factor of ten.

Abstract translation: 一种用于计算设备失配变化对电路性能变化的贡献的系统，方法和计算机程序产品。 实施例估计了模拟电路设计中的哪些单独设备对电路性能的影响最大，同时比传统的多元线性回归要少得多的仿真。 有序指标在线性模型中为每个输入失配参数分配输出方差贡献。 这些实施例总结了每个设备中的输出差异，并且基于总结的贡献对不匹配贡献进行排序。 额外的灵敏度分析可以得出最终的精确线性贡献。 实施例可以将所需的模拟量减少10倍。