公开(公告)号：US09928318B1

公开(公告)日：2018-03-27

申请号：US15142694

申请日：2016-04-29

Applicant: Cadence Design Systems, Inc.

Inventor： Taranjit Singh Kukal ,  Kumar Chidhambara Keshavan ,  Bradford Chastain Griffin ,  Kenneth R. Willis ,  Shivani Sharma ,  Ambrish Kant Varma ,  Xuegang Zeng

IPC: G06F17/00 ,  G06F17/50

CPC classification number: G06F17/5009

Abstract: The present disclosure relates to a system and method for simulating channels in an electronic circuit design. Embodiments may include receiving, at one or more computing devices, an electronic circuit design including at least one channel. Embodiments may further include transmitting two or more inputs from two or more transmitter drivers on two or more wires to the at least one channel. In some embodiments, the inputs may be distributed across the wires based upon a chordal code. Embodiments may also include generating simulated waveforms based upon the inputs. Embodiments may further include transmitting the simulated waveforms from the channel on the wires to a comparator block. Embodiments may also include comparing the simulated waveforms on the wires at the comparator block to produce two or more simulated outputs. Embodiments may include transmitting the simulated outputs from the comparator block on the wires to two or more post-comparator receivers.

公开(公告)号：US10540464B1

公开(公告)日：2020-01-21

申请号：US16103888

申请日：2018-08-14

Applicant: Cadence Design Systems, Inc.

Inventor： Suketu Desai ,  Anshu Mani ,  Apurva Soni ,  Shivani Sharma ,  Avnish Varma ,  Xin Gu

IPC: G06F17/50

Abstract: The present embodiments relate to critical path aware voltage drop analysis. A method can include identifying a number of cell instances with largest individual power consumption values. The method can include identifying, by performing static timing analysis, a first number of circuit timing paths of an integrated circuit design with largest timing violations. The method can include identifying, by performing the static timing analysis, a second number of circuit timing paths of the integrated circuit design. Each of the second number of circuit timing paths has a timing violation and is formed by one or more of the identified number of cell instances. The method can include generating logic state toggle vectors by propagating logic states through the first and second numbers of circuit timing paths. The method can include performing voltage drop analysis on the integrated circuit design using the generated logic state toggle vectors.