公开(公告)号：US09881120B1

公开(公告)日：2018-01-30

申请号：US14871735

申请日：2015-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Arnold Ginetti ,  Steven Durrill ,  Taranjit Singh Kukal

IPC: G06F17/50 ,  G06F7/76 ,  G06F1/26 ,  G06F15/78

CPC classification number: G06F17/5081 ,  G06F1/266 ,  G06F7/76 ,  G06F15/7867 ,  G06F17/5018 ,  G06F17/5036 ,  G06F17/505 ,  G06F17/5054 ,  G06F17/5063 ,  G06F2217/80 ,  H01L23/50 ,  H05K1/0203 ,  H05K3/0005

Abstract: Various embodiments implementing a multi-fabric mixed-signal electronic system design spanning across multiple design fabrics with electrical and/or thermal analysis awareness. A schematic design may be extracted from and a power delivery network (PDN) model may be determined from a plurality of layouts in multiple design fabrics in a multi-fabric design environment platform. A PDN-aware, multi-fabric full system schematic may be constructed by assembling the PDN model and the schematic design into the PDN-aware, multi-fabric full system schematic. For a schematic generated for a circuit block of interest, chip power models may be determined for the remaining portion of the multi-fabric mixed-signal electronic system design, and the PDN-aware, multi-fabric full system schematic may be updated by accounting for the chip power models. The circuit block of interest may then be electrically and/or thermally analyzed within the context of the remaining portion.

公开(公告)号：US09798848B1

公开(公告)日：2017-10-24

申请号：US14475469

申请日：2014-09-02

Applicant: Cadence Design Systems, inc.

Inventor： Kumar Chidhambara Keshavan ,  Ambrish Kant Varma ,  Taranjit Singh Kukal ,  Rameet Pal ,  Bradford Griffin ,  Kenneth Robert Willis ,  Hui Qi ,  Xuegang Zeng

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: Disclosed are methods and systems for characterizing and analyzing an electronic system design including a parallel interface. Some methods and systems identify an electronic design including a parallel interface, determine a single circuit representation including the parallel interface from the electronic design, and analyze the parallel interface to determine waveform responses of the parallel interface by using channel analysis techniques without performing circuit simulations. Some other methods and systems are directed at performing channel analyses for a communication interface of an electronic system by concurrently applying stimuli to corresponding transmitters of a communication interface, characterizing the communication interface to perform a single simulation on the communication interface with the stimulus to determine responses at receivers of the communication interface, and determining waveform responses of the communication interface by performing operations on the responses and an input signal to the communication interface.

公开(公告)号：US20160063171A1

公开(公告)日：2016-03-03

申请号：US14476365

申请日：2014-09-03

Applicant: Cadence Design Systems, Inc.

Inventor： Alok Tripathi ,  An-yu Kuo ,  Bradley Brim ,  Taranjit Singh Kukal

IPC: G06F17/50 ,  G05B19/418

CPC classification number: G05B19/418 ,  G06F17/5063 ,  G06F17/5068 ,  G06F2217/74 ,  G06F2217/80 ,  G06F2217/82 ,  Y02P90/26 ,  Y02P90/265

Abstract: Disclosed are methods and systems for by identifying or generating an electrical schematic, generating a thermal schematic by associating thermal RC circuits of the electronic design with the electrical schematic, performing at least two analyses of an electrical analysis, a thermal analysis, and an electromagnetic interference compliance (EMC) analysis with the electrical schematic and the thermal schematic of the electronic design. The electrical, thermal, and EMC analyses may be performed concurrently by forwarding intermediate or final analysis results to each other, and the analysis results may be presented simultaneously in one or more user interface windows. The thermal schematic may be obtained by extracting the thermal RC circuits, identifying corresponding electrical circuit components that correspond to the extracted thermal RC circuits, and importing the thermal RC circuits into the electrical schematic so that the electrical and thermal schematics have the same nodes.

Abstract translation: 公开了通过识别或产生电气原理图的方法和系统，通过将电子设计的热RC电路与电气原理图相关联来产生热示意图，执行电分析，热分析和电磁干扰的至少两个分析 电磁兼容性（EMC）分析与电气原理图和电子设计的原理图。 可以通过将中间或最终分析结果彼此转发来同时执行电，热和EMC分析，并且可以在一个或多个用户界面窗口中同时呈现分析结果。 可以通过提取热RC电路，识别与提取的热RC电路相对应的相应的电路部件，并将热RC电路导入电气原理图，使得电气和热图具有相同的节点，可以获得热图。

公开(公告)号：US11354477B1

公开(公告)日：2022-06-07

申请号：US17143371

申请日：2021-01-25

Applicant: Cadence Design Systems, Inc.

Inventor： Jasleen Kaur Ahuja ,  Taranjit Singh Kukal ,  Vikrant Khanna ,  Nikhil Gupta ,  Rohit Shukla ,  Kunal Gupta ,  Charu Kapoor

IPC: G06F30/00 ,  G06F30/392 ,  G06F30/3953 ,  H01F27/06

Abstract: Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving a printed circuit board schematic and one or more electronic circuits. Embodiments may further include automatically generating, one or more circuit templates based upon, at least in part, the printed circuit board schematic and one or more electronic circuits. The one or more circuit templates may be stored at an electronic design database. Embodiments may also include receiving a current printed circuit board schematic and automatically determining whether a subcircuit of the current printed circuit board schematic is an exact or approximate match with the one or more circuit templates.

公开(公告)号：US10678978B1

公开(公告)日：2020-06-09

申请号：US15721853

申请日：2017-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Taranjit Singh Kukal ,  Arnold Jean Marie Gustave Ginetti ,  Madhur Sharma ,  Balvinder Singh

IPC: G06F17/50 ,  G06F30/31 ,  H05K3/00 ,  G06F30/33 ,  G06F30/398 ,  G06F30/337 ,  G06F30/3308 ,  G06F30/373 ,  G06F30/367 ,  G06F111/20 ,  G06F111/12

Abstract: Disclosed are methods, systems, and articles of manufacture for binding and annotating an electronic design with a schematic driven extracted view. These techniques identify a schematic design and an extracted view of an electronic design and bind the schematic design with the extracted view. The resulting binding information concerning binding the schematic design with the extracted view is stored in a data structure. The schematic design may be annotated with extracted view information pertaining to the extracted view based at least in part upon the binding information. A response to a user action may be automatically generated based in part or in whole upon the extracted view information or the binding information.

公开(公告)号：US10467370B1

公开(公告)日：2019-11-05

申请号：US15721851

申请日：2017-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Taranjit Singh Kukal ,  Arnold Jean Marie Gustave Ginetti ,  Preeti Chauhan ,  Nikhil Gupta ,  Vikas Aggarwal ,  Vikrant Khanna

IPC: G06F17/50 ,  H05K3/00

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing a schematic circuit design component as a transmission line model in a schematic driven extracted view for an electronic design. These techniques identify a schematic circuit component design form a schematic design of an electronic design and identify or determine layout device information of a layout circuit component design corresponding to the schematic circuit component design. An extracted view may be generated or identified for the electronic design at least by using a transmission line model based in part or in whole upon connectivity information or a hierarchical structure of the electronic design. The electronic design may then be modified or updated based in part or in whole upon results of performing one or more analyses on the extracted view with the transmission line model.

公开(公告)号：US09454634B1

公开(公告)日：2016-09-27

申请号：US14588279

申请日：2014-12-31

Applicant: Cadence Design Systems, Inc.

Inventor： Taranjit Singh Kukal ,  Surender Singh ,  Avinash Singh

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5068 ,  G06F17/5072

Abstract: Disclosed are mechanisms for implementing an IC package layout design with an integrated circuit package design estimator. These mechanisms determine an estimated number of layers for an integrated circuit (IC) package design including one or more IC die designs, determine whether the estimated number of layers suffice to accommodate routing demands for the IC package layout design, determine a power layer and/or a ground layer based in part or in whole upon one or more factors, and generate an output for the IC package layout design based using at least the estimated number of layers and the power layer and/or the ground layer. These mechanisms use input including connectivity information, thermal effects, and/or IC placement information to determine estimates for the total number of layers, layer stack-up, power and ground plane assignment, and via libraries to guide IC package layout design.

Abstract translation: 公开了用于利用集成电路封装设计估计器实现IC封装布局设计的机制。 这些机制确定包括一个或多个IC芯片设计的集成电路（IC）封装设计的估计数量的层，确定估计的层数是否足以适应IC封装布局设计的路由需求，确定功率层和/ 或基于一个或多个因素的部分或全部的接地层，并且至少使用估计的层数和功率层和/或接地层来生成用于IC封装布局设计的输出。 这些机制使用输入，包括连接信息，热效应和/或IC放置信息，以确定总层数，层叠，电源和接地平面分配的估计，以及通过库来指导IC封装布局设计。

公开(公告)号：US10558780B1

公开(公告)日：2020-02-11

申请号：US15721845

申请日：2017-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Taranjit Singh Kukal ,  Arnold Jean Marie Gustave Ginetti ,  Jagdish Lohani ,  Harmohan Singh ,  Ritabrata Bhattacharya ,  Balvinder Singh

IPC: G06F17/50 ,  H05K3/00

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing schematic driven extracted views for an electronic design. These techniques identify a schematic circuit component design represented by a schematic symbol from a schematic design and identifying layout device information from a layout of the electronic design. An extracted view is generated anew or updated from an existing extracted view at least by placing and interconnecting a symbol in the schematic design based at least in part upon the layout device information. The electronic design may be further updated based in part or in whole upon results of performing one or more analyses on the extracted view.

公开(公告)号：US10289793B1

公开(公告)日：2019-05-14

申请号：US15445002

申请日：2017-02-28

Applicant: Cadence Design Systems, Inc.

Inventor： Taranjit Singh Kukal ,  Arnold Jean Marie Gustave Ginetti ,  Steven Roberts Durrill

IPC: G06F17/50

Abstract: Embodiments include herein are directed towards a method for use in an electronic design environment is provided. The method may include receiving, using a processor, a parent fabric corresponding to a top layout fabric associated with an electronic design and receiving a child fabric corresponding to a child layout fabric associated with the electronic design. The method may further include receiving an electromagnetic (“EM”) model that represents one or more cross-fabric geometries associated with the electronic design and generating a hierarchical schematic representing each layout fabric, wherein the EM model is inserted into a parent schematic. The method may also include managing one or more interface connections between the hierarchical schematic.

公开(公告)号：US09934354B1

公开(公告)日：2018-04-03

申请号：US15205593

申请日：2016-07-08

Applicant: Cadence Design Systems, Inc.

Inventor： Taranjit Singh Kukal ,  Balvinder Singh ,  Steven R. Durrill ,  Arnold Ginetti ,  Vikrant Khanna ,  Abhishek Dabral ,  Madhur Sharma ,  Nikhil Gupta ,  Ritabrata Bhattacharya

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5009 ,  G06F17/5077 ,  G06F2217/40 ,  G06F2217/74

Abstract: Disclosed are techniques for implementing a layout-driven, multi-fabric schematic design of an electronic design. These techniques identify a multi-fabric layout spanning across multiple design fabrics and layout connectivity information and determine a device map that correlates a first set of devices in the multi-fabric layout with respective parasitic models. The device map can be identified one or more pre-existing device maps or can be constructed anew. A multi-fabric schematic can be generated by using at least the respective parasitic models and the layout connectivity information.