公开(公告)号：US10387595B1

公开(公告)日：2019-08-20

申请号：US15590914

申请日：2017-05-09

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Anshu Mani ,  Avnish Varma ,  Suketu Desai

IPC: G06F17/50

Abstract: Disclosed herein are embodiments of systems and methods for a deterministic modeling of integrated clock gate (ICG) activity in a vectorless power analysis of a synthesized integrated circuit (IC) design. The systems and methods may generate a priority list of the ICGs based on the slack values of the outputs of the ICGs calculated from a static timing analysis (STA). The system and method may further receive one or more priority inputs from the user and select the ICGs to be activated during power analysis based on the priority list and the priority inputs from the user. The systems and methods may propagate a set of state stimuli through the output cones of the selected ICGs and calculate the current through and power consumed by circuit devices in the output cones based on the state propagation and global data activity.

公开(公告)号：US10540464B1

公开(公告)日：2020-01-21

申请号：US16103888

申请日：2018-08-14

Applicant: Cadence Design Systems, Inc.

Inventor： Suketu Desai ,  Anshu Mani ,  Apurva Soni ,  Shivani Sharma ,  Avnish Varma ,  Xin Gu

IPC: G06F17/50

Abstract: The present embodiments relate to critical path aware voltage drop analysis. A method can include identifying a number of cell instances with largest individual power consumption values. The method can include identifying, by performing static timing analysis, a first number of circuit timing paths of an integrated circuit design with largest timing violations. The method can include identifying, by performing the static timing analysis, a second number of circuit timing paths of the integrated circuit design. Each of the second number of circuit timing paths has a timing violation and is formed by one or more of the identified number of cell instances. The method can include generating logic state toggle vectors by propagating logic states through the first and second numbers of circuit timing paths. The method can include performing voltage drop analysis on the integrated circuit design using the generated logic state toggle vectors.

公开(公告)号：US10586000B1

公开(公告)日：2020-03-10

申请号：US16130027

申请日：2018-09-13

Applicant: Cadence Design Systems, Inc.

Inventor： Anshu Mani ,  Bhuvnesh Kumar ,  Xin Gu

IPC: G06F17/50

Abstract: The present disclosure relates to modeling the transient current of a partially simulated hierarchical gate-level electronic design. Embodiments may include providing a partially simulated hierarchical gate-level electronic design, wherein the design includes a design hierarchy having one or more leaf blocks associated therewith. Embodiments may also include identifying activity of sequential elements of the leaf blocks using simulation vectors, wherein the activity is used to estimate an amount of current associated with the sequential elements. Embodiments may further include computing an adaptive activity of a parent block of the leaf blocks, wherein the adaptive activity of the parent block corresponds to a weighted average of known activity of leaf blocks. Embodiments may also include generating an adaptive activity of a top block of the leaf blocks based upon the adaptive activity of the parent block and performing a mixed-mode simulation based upon the adaptive activity of the top block.

公开(公告)号：US10460055B1

公开(公告)日：2019-10-29

申请号：US15955497

申请日：2018-04-17

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Yuvaraj Gogoi ,  Bhuvnesh Kumar ,  Anshu Mani ,  Suketu Desai

IPC: G06F17/50

Abstract: A computer performing a transient vectorless power analysis of a multi-clock domain integrated circuit (IC) design may execute a scheduling cycle based on the dominant clock frequency and schedule events based on comparing instance clock frequencies with the dominant clock frequency. If the instance clock frequency matches the dominant clock frequency, the computer may schedule a single event per scheduling cycle for the sequential circuit devices driven by the respective instance clocks. If the instance clock frequency is faster than the dominant clock frequency, the computer may schedule number of events per scheduling cycle based on the ratio of the instance clock frequency to the dominant clock frequency. If the instance clock frequency is less than the dominant clock frequency, the computer may schedule a single event per scheduling cycle if the computer determines that there is a triggering edge of the instance clock within the scheduling cycle.