公开(公告)号：US09646120B1

公开(公告)日：2017-05-09

申请号：US15158933

申请日：2016-05-19

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Beshara Elmufdi ,  Mitchell G. Poplack ,  Viktor Salitrennik

IPC: G06F17/50

CPC classification number: G06F17/5027 ,  G06F2217/68 ,  G06F2217/86

Abstract: The present patent document relates to a method to compact trace data generated by emulation processors during emulation of a circuit design, and a hardware functional verification system that compacts trace data. Compaction logic within emulation processor clusters accumulated data bits output from the emulation processors and compacts them into trace data bytes in registers based on enable bits identifying valid trace data according to a compaction scheme. Trace data bytes are further accumulated and compacted into larger trace data bytes in higher level processor clusters of the emulation chip according to a compaction hierarchy, with the compacted trace data bytes stored into a trace array of the emulation chip.

公开(公告)号：US09171111B1

公开(公告)日：2015-10-27

申请号：US14500913

申请日：2014-09-29

Applicant: Cadence Design Systems, Inc.

Inventor： Beshara Elmufdi ,  Mitchell G. Poplack ,  Viktor Salitrennik

IPC: G06F17/50

CPC classification number: G06F17/5027 ,  G06F2217/68 ,  G06F2217/86

Abstract: A processor-based hardware functional verification system with time shift registers is described. The system includes a processor cluster with a plurality of processors that each have a data inputs and select inputs. Furthermore, a plurality of electronic memories each having a plurality of read ports is associated with the processors, respectively. The time shift registers each have an input in communication with the read ports of the electronic memories and an output in communication with the select inputs of the processors. The system further includes an instruction memory that provides a control signal to each of the time shift registers to store data output from read ports of the electronic memories that can be provided to the processor for evaluation during a subsequent emulation step.

Abstract translation: 描述了具有时移寄存器的基于处理器的硬件功能验证系统。 该系统包括具有多个处理器的处理器集群，每个处理器具有数据输入和选择输入。 此外，分别具有多个读取端口的多个电子存储器与处理器相关联。 时移寄存器各自具有与电子存储器的读取端口通信的输入和与处理器的选择输入通信的输出。 该系统还包括指令存储器，其向每个时移寄存器提供控制信号，以存储从可以提供给处理器的电子存储器的读端口输出的数据，用于在随后的仿真步骤期间进行评估。

公开(公告)号：US09372947B1

公开(公告)日：2016-06-21

申请号：US14500899

申请日：2014-09-29

Applicant: Cadence Design Systems, Inc.

Inventor： Beshara Elmufdi ,  Mitchell G. Poplack ,  Viktor Salitrennik

IPC: G06F17/50

CPC classification number: G06F17/5027 ,  G06F2217/68 ,  G06F2217/86

Abstract: The present patent document relates to a method to compact trace data generated by emulation processors during emulation of a circuit design, and a hardware functional verification system that compacts trace data. Compaction logic within emulation processor clusters accumulated data bits output from the emulation processors and compacts them into trace data bytes in registers based on enable bits identifying valid trace data according to a compaction scheme. Trace data bytes are further accumulated and compacted into larger trace data bytes in higher level processor clusters of the emulation chip according to a compaction hierarchy, with the compacted trace data bytes stored into a trace array of the emulation chip.

Abstract translation: 本专利文献涉及一种在仿真电路设计期间压缩由仿真处理器产生的跟踪数据的方法，以及压缩跟踪数据的硬件功能验证系统。 仿真处理器集群内的压缩逻辑累积从仿真处理器输出的数据位，并根据压缩方案，根据使能位识别有效跟踪数据将它们压缩成寄存器中的跟踪数据字节。 根据压缩层级，跟踪数据字节进一步累积并压缩成仿真芯片的较高级处理器集群中较大的跟踪数据字节，压缩的跟踪数据字节存储在仿真芯片的跟踪阵列中。

公开(公告)号：US10509877B1

公开(公告)日：2019-12-17

申请号：US15374508

申请日：2016-12-09

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Mitchell G. Poplack ,  Viktor Salitrennik ,  Gavin Zawalski

IPC: G06F9/455 ,  G06F17/50

Abstract: Systems, methods, and products having pipelined inputs to and outputs from an emulator are disclosed. Using a pipeline may allow the round trip cable delay (RTCD) to be spread across two or more clock cycles. In an embodiment, an emulation system may store input data received from a target device during a first clock cycle at a target timing domain interfacing component (TTD), and transmit the stored input data during a second clock cycle after the first clock cycle. In another embodiment, the emulation system may delay transmitting the input data received at the TTD during the first clock cycle such that that the input data reaches the emulator at a predetermined time during the second clock cycle. As the RTCD is spread across multiple clock cycles, the emulation system may implement faster clocks.

公开(公告)号：US09298866B1

公开(公告)日：2016-03-29

申请号：US14501699

申请日：2014-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Beshara Elmufdi ,  Mitchell G. Poplack ,  Viktor Salitrennik

IPC: G06F17/50

CPC classification number: G06F17/5027 ,  G06F17/5022 ,  G06F2217/86

Abstract: The present patent document relates to a method and apparatus for modeling a flip-flop of a user's circuit design when that circuit design is mapped in a hardware functional verification system including a plurality of interconnected emulation chips, or in a single emulation chip. The flip flop can be modeled in the emulation chip as two stages using only a single instruction, and may be configured by programming a register set. A data block, enable block, and LUT block are provided to model the flip flop, and may operate in one of several modes, including combined and uncombined modes. The data block includes a data array to store and provide previous data inputs and previous states of the modeled flip flop. The disclosed embodiments allow a more efficient use of LUTs for modeling flip flops, including options for resets and global enables, operating in several modes.

Abstract translation: 本专利文献涉及当该电路设计被映射到包括多个互连的仿真芯片的硬件功能验证系统中时，或者在单个仿真芯片中时，用于对用户电路设计的触发器进行建模的方法和装置。 触发器可以在仿真芯片中被建模为仅使用单个指令的两个阶段，并且可以通过对寄存器集进行编程来配置。 提供数据块，使能块和LUT块以对触发器建模，并且可以在多种模式之一中操作，包括组合和未组合模式。 数据块包括用于存储并提供先前数据输入和建模触发器的先前状态的数据阵列。 所公开的实施例允许更有效地使用LUT来建模触发器，包括在多种模式下操作的复位和全局启用的选项。

公开(公告)号：US09292639B1

公开(公告)日：2016-03-22

申请号：US14529076

申请日：2014-10-30

Applicant: Cadence Design Systems, Inc.

Inventor： Beshara Elmufdi ,  Viktor Salitrennik ,  Mitchell G. Poplack

IPC: G06F17/50 ,  G06F12/08 ,  G06F12/02 ,  G06F12/06

CPC classification number: G06F17/5027 ,  G06F12/02 ,  G06F12/06 ,  G06F12/08

Abstract: A method and system of providing additional lookup tables in an emulation processor cluster of an emulation chip of a hardware functional verification system is provided. An indirection table may be used within the processor cluster to provide the commonly-used function tables for the lookup tables (LUTs). The indirection table may be indexed according to a smaller portion of the standard LUT function table provided by an instruction than otherwise needed. The unused function table bits in the instruction may then be used for other purposes, including providing functionality to one or more extra LUTs of the processor cluster, whose function tables may be provided from another indirection table provided for that purpose. Additional processing capacity may thereby be provided for the cluster with a small amount of additional overhead within the emulation chip, while still providing the full range of function tables of the LUTs.

Abstract translation: 提供了一种在硬件功能验证系统的仿真芯片的仿真处理器集群中提供附加查找表的方法和系统。 可以在处理器集群内使用间接表来为查找表（LUT）提供常用的功能表。 间接表可以根据由指令提供的标准LUT功能表的较小部分进行索引，而不是另外需要。 然后，指令中的未使用的功能表位可以用于其他目的，包括向处理器集群的一个或多个额外LUT提供功能，其功能表可以由为此目的而设置的另一个间接表提供。 从而可以为仿真芯片内的少量额外开销的集群提供额外的处理能力，同时仍然提供LUT的全部范围的功能表。