公开(公告)号：US10534625B1

公开(公告)日：2020-01-14

申请号：US15064418

申请日：2016-03-08

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Beshara Elmufdi

IPC: G06F9/455

Abstract: Disclosed herein is an apparatus and method for emulating hardware. The apparatus includes a data array configured to store input data for an emulation cycle and a carry chain coupled to the data array receives one or more inputs from the data array. The carry chain is configured to generate output data in response to performing an arithmetic operation by a set of configurable logic gates using the one or more inputs in a pre-determined number of clock cycles. One or more processors are coupled to the carry chain and the data array, and are configured to emulate a logic gate function using at least the input data from the data array or the output data from the carry chain.

公开(公告)号：US09910810B1

公开(公告)日：2018-03-06

申请号：US14921424

申请日：2015-10-23

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Mitchell G. Poplack ,  Yuhei Hayashi ,  Beshara Elmufdi

IPC: G06F13/00 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4068 ,  G06F13/4282

Abstract: Systems and methods of emulating application-specific integrated circuits using multiple execution phases, where different inputs and outputs are used or produced by components of the emulation system are disclosed. For example, an OMUX may select and transmit different data over a serial bus based on the execution phase of the emulator system. In another example, a processor or cluster may capture outputted data during a first execution phase, execute instructions for a second execution phase, and then return to the capture outputted data for further processing during a next cycle of the first execution phase.

公开(公告)号：US09646120B1

公开(公告)日：2017-05-09

申请号：US15158933

申请日：2016-05-19

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Beshara Elmufdi ,  Mitchell G. Poplack ,  Viktor Salitrennik

IPC: G06F17/50

CPC classification number: G06F17/5027 ,  G06F2217/68 ,  G06F2217/86

Abstract: The present patent document relates to a method to compact trace data generated by emulation processors during emulation of a circuit design, and a hardware functional verification system that compacts trace data. Compaction logic within emulation processor clusters accumulated data bits output from the emulation processors and compacts them into trace data bytes in registers based on enable bits identifying valid trace data according to a compaction scheme. Trace data bytes are further accumulated and compacted into larger trace data bytes in higher level processor clusters of the emulation chip according to a compaction hierarchy, with the compacted trace data bytes stored into a trace array of the emulation chip.

公开(公告)号：US09298866B1

公开(公告)日：2016-03-29

申请号：US14501699

申请日：2014-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Beshara Elmufdi ,  Mitchell G. Poplack ,  Viktor Salitrennik

IPC: G06F17/50

CPC classification number: G06F17/5027 ,  G06F17/5022 ,  G06F2217/86

Abstract: The present patent document relates to a method and apparatus for modeling a flip-flop of a user's circuit design when that circuit design is mapped in a hardware functional verification system including a plurality of interconnected emulation chips, or in a single emulation chip. The flip flop can be modeled in the emulation chip as two stages using only a single instruction, and may be configured by programming a register set. A data block, enable block, and LUT block are provided to model the flip flop, and may operate in one of several modes, including combined and uncombined modes. The data block includes a data array to store and provide previous data inputs and previous states of the modeled flip flop. The disclosed embodiments allow a more efficient use of LUTs for modeling flip flops, including options for resets and global enables, operating in several modes.

Abstract translation: 本专利文献涉及当该电路设计被映射到包括多个互连的仿真芯片的硬件功能验证系统中时，或者在单个仿真芯片中时，用于对用户电路设计的触发器进行建模的方法和装置。 触发器可以在仿真芯片中被建模为仅使用单个指令的两个阶段，并且可以通过对寄存器集进行编程来配置。 提供数据块，使能块和LUT块以对触发器建模，并且可以在多种模式之一中操作，包括组合和未组合模式。 数据块包括用于存储并提供先前数据输入和建模触发器的先前状态的数据阵列。 所公开的实施例允许更有效地使用LUT来建模触发器，包括在多种模式下操作的复位和全局启用的选项。

公开(公告)号：US09292640B1

公开(公告)日：2016-03-22

申请号：US14529090

申请日：2014-10-30

Applicant: Cadence Design Systems, Inc.

Inventor： Beshara Elmufdi ,  Mitchell G. Poplack ,  Viktor Salittrennik

IPC: G06F17/50 ,  G06F12/12 ,  G06F12/08

CPC classification number: G06F17/5027 ,  G06F12/08 ,  G06F12/121

Abstract: A method and system of dynamically selecting a memory read port are provided. In one form a method may comprises, in part, processing instructions in the emulation processors of a hardware functional verification system, storing output bits generated by the LUT in a plurality of storage elements, selecting between a plurality of previously-stored LUT output bits and the output port of the data memory, selecting one of the plurality of output bits stored in the storage elements, and sending the current data bit provided at the output port of the data memory to a selection circuit when previously-stored LUT output bits are provided. The disclosed systems and methods provide the ability all inputs to a LUT, even while a memory read port is occupied performing other operations during that emulation step, for example sending a value stored in the memory to another emulation processor using the selection circuit.

Abstract translation: 提供动态选择存储器读端口的方法和系统。 在一种形式中，方法可以部分地包括处理硬件功能验证系统的仿真处理器中的指令，将由LUT生成的输出位存储在多个存储元件中，在多个先前存储的LUT输出位之间进行选择 数据存储器的输出端口，选择存储在存储元件中的多个输出位之一，以及当预先存储的LUT输出位被提供时，将提供在数据存储器的输出端口处的当前数据位发送到选择电路 。 所公开的系统和方法提供了对LUT的所有输入的能力，即使当存储器读取端口被占用在该仿真步骤期间执行其他操作时，例如，使用该选择电路将存储在存储器中的值发送到另一个仿真处理器。

公开(公告)号：US09292639B1

公开(公告)日：2016-03-22

申请号：US14529076

申请日：2014-10-30

Applicant: Cadence Design Systems, Inc.

Inventor： Beshara Elmufdi ,  Viktor Salitrennik ,  Mitchell G. Poplack

IPC: G06F17/50 ,  G06F12/08 ,  G06F12/02 ,  G06F12/06

CPC classification number: G06F17/5027 ,  G06F12/02 ,  G06F12/06 ,  G06F12/08

Abstract: A method and system of providing additional lookup tables in an emulation processor cluster of an emulation chip of a hardware functional verification system is provided. An indirection table may be used within the processor cluster to provide the commonly-used function tables for the lookup tables (LUTs). The indirection table may be indexed according to a smaller portion of the standard LUT function table provided by an instruction than otherwise needed. The unused function table bits in the instruction may then be used for other purposes, including providing functionality to one or more extra LUTs of the processor cluster, whose function tables may be provided from another indirection table provided for that purpose. Additional processing capacity may thereby be provided for the cluster with a small amount of additional overhead within the emulation chip, while still providing the full range of function tables of the LUTs.

Abstract translation: 提供了一种在硬件功能验证系统的仿真芯片的仿真处理器集群中提供附加查找表的方法和系统。 可以在处理器集群内使用间接表来为查找表（LUT）提供常用的功能表。 间接表可以根据由指令提供的标准LUT功能表的较小部分进行索引，而不是另外需要。 然后，指令中的未使用的功能表位可以用于其他目的，包括向处理器集群的一个或多个额外LUT提供功能，其功能表可以由为此目的而设置的另一个间接表提供。 从而可以为仿真芯片内的少量额外开销的集群提供额外的处理能力，同时仍然提供LUT的全部范围的功能表。

公开(公告)号：US09372947B1

公开(公告)日：2016-06-21

申请号：US14500899

申请日：2014-09-29

Applicant: Cadence Design Systems, Inc.

Inventor： Beshara Elmufdi ,  Mitchell G. Poplack ,  Viktor Salitrennik

IPC: G06F17/50

CPC classification number: G06F17/5027 ,  G06F2217/68 ,  G06F2217/86

Abstract: The present patent document relates to a method to compact trace data generated by emulation processors during emulation of a circuit design, and a hardware functional verification system that compacts trace data. Compaction logic within emulation processor clusters accumulated data bits output from the emulation processors and compacts them into trace data bytes in registers based on enable bits identifying valid trace data according to a compaction scheme. Trace data bytes are further accumulated and compacted into larger trace data bytes in higher level processor clusters of the emulation chip according to a compaction hierarchy, with the compacted trace data bytes stored into a trace array of the emulation chip.

Abstract translation: 本专利文献涉及一种在仿真电路设计期间压缩由仿真处理器产生的跟踪数据的方法，以及压缩跟踪数据的硬件功能验证系统。 仿真处理器集群内的压缩逻辑累积从仿真处理器输出的数据位，并根据压缩方案，根据使能位识别有效跟踪数据将它们压缩成寄存器中的跟踪数据字节。 根据压缩层级，跟踪数据字节进一步累积并压缩成仿真芯片的较高级处理器集群中较大的跟踪数据字节，压缩的跟踪数据字节存储在仿真芯片的跟踪阵列中。

公开(公告)号：US09852807B1

公开(公告)日：2017-12-26

申请号：US14972690

申请日：2015-12-17

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Beshara Elmufdi

IPC: G06F13/10 ,  G11C29/38 ,  G11C29/36

CPC classification number: G11C15/04 ,  G11C29/54

Abstract: Disclosed herein are components of an emulation system capable of efficiently recreating the functionality a CAM/TCAM memory circuit. Rather than using specialized gates or the existing processors, the embodiments described herein configure/instruct the existing memory circuits of the emulation system to imitate a search engine function that queries the existing RAM circuits, portions of which are reconfigured to function as CAM/TCAM memory. The hardware-based search engine and the repurposed memory (e.g., RAM, SRAM, DRAM) allow an emulation system to emulate the functionality of a CAM/TCAM memory. This can be implemented at a low processing cost to the emulation system, as it provides the ability to store more CAM/TCAM data at a very low cost. It can also use the existing system and emulation buses that other components (e.g., processors) of the system use to communicate with the memory, so expansion of the emulation system may not be required.

公开(公告)号：US09171111B1

公开(公告)日：2015-10-27

申请号：US14500913

申请日：2014-09-29

Applicant: Cadence Design Systems, Inc.

Inventor： Beshara Elmufdi ,  Mitchell G. Poplack ,  Viktor Salitrennik

IPC: G06F17/50

CPC classification number: G06F17/5027 ,  G06F2217/68 ,  G06F2217/86

Abstract: A processor-based hardware functional verification system with time shift registers is described. The system includes a processor cluster with a plurality of processors that each have a data inputs and select inputs. Furthermore, a plurality of electronic memories each having a plurality of read ports is associated with the processors, respectively. The time shift registers each have an input in communication with the read ports of the electronic memories and an output in communication with the select inputs of the processors. The system further includes an instruction memory that provides a control signal to each of the time shift registers to store data output from read ports of the electronic memories that can be provided to the processor for evaluation during a subsequent emulation step.

Abstract translation: 描述了具有时移寄存器的基于处理器的硬件功能验证系统。 该系统包括具有多个处理器的处理器集群，每个处理器具有数据输入和选择输入。 此外，分别具有多个读取端口的多个电子存储器与处理器相关联。 时移寄存器各自具有与电子存储器的读取端口通信的输入和与处理器的选择输入通信的输出。 该系统还包括指令存储器，其向每个时移寄存器提供控制信号，以存储从可以提供给处理器的电子存储器的读端口输出的数据，用于在随后的仿真步骤期间进行评估。

公开(公告)号：US10409624B1

公开(公告)日：2019-09-10

申请号：US15064273

申请日：2016-03-08

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Beshara Elmufdi

IPC: G06F9/455

Abstract: Disclosed herein are systems and methods of an emulation system. A hardware emulator of an emulation system includes one or more processors configured to generate data in an emulation cycle. Each bit of the generated data is associated with a tag. The hardware emulator may include a compaction unit configured to receive the data generated by the one or more processors, and select one or more bits from total bits of the data based on valid tags associated with the bits of the data. The hardware emulator further includes a data array comprising non-transitory machine-readable storage media configured to store the one or more bits of the data received from the compaction unit.