公开(公告)号：US09292640B1

公开(公告)日：2016-03-22

申请号：US14529090

申请日：2014-10-30

Applicant: Cadence Design Systems, Inc.

Inventor： Beshara Elmufdi ,  Mitchell G. Poplack ,  Viktor Salittrennik

IPC: G06F17/50 ,  G06F12/12 ,  G06F12/08

CPC classification number: G06F17/5027 ,  G06F12/08 ,  G06F12/121

Abstract: A method and system of dynamically selecting a memory read port are provided. In one form a method may comprises, in part, processing instructions in the emulation processors of a hardware functional verification system, storing output bits generated by the LUT in a plurality of storage elements, selecting between a plurality of previously-stored LUT output bits and the output port of the data memory, selecting one of the plurality of output bits stored in the storage elements, and sending the current data bit provided at the output port of the data memory to a selection circuit when previously-stored LUT output bits are provided. The disclosed systems and methods provide the ability all inputs to a LUT, even while a memory read port is occupied performing other operations during that emulation step, for example sending a value stored in the memory to another emulation processor using the selection circuit.

Abstract translation: 提供动态选择存储器读端口的方法和系统。 在一种形式中，方法可以部分地包括处理硬件功能验证系统的仿真处理器中的指令，将由LUT生成的输出位存储在多个存储元件中，在多个先前存储的LUT输出位之间进行选择 数据存储器的输出端口，选择存储在存储元件中的多个输出位之一，以及当预先存储的LUT输出位被提供时，将提供在数据存储器的输出端口处的当前数据位发送到选择电路 。 所公开的系统和方法提供了对LUT的所有输入的能力，即使当存储器读取端口被占用在该仿真步骤期间执行其他操作时，例如，使用该选择电路将存储在存储器中的值发送到另一个仿真处理器。