公开(公告)号：US09501598B1

公开(公告)日：2016-11-22

申请号：US14493240

申请日：2014-09-22

Applicant: Cadence Design Systems, Inc.

Inventor： Donald J. O'Riordan ,  Vuk Borich ,  Keith Dennison

IPC: G06F17/50

CPC classification number: G06F17/5063 ,  G06F17/5036 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/00

Abstract: A system and method for managing analog assertion publication and re-use for analog and mixed-signal circuit designs. A graphical user interface based environment allows circuit designers to create, verify, formalize, and publish an analog assertion for a circuit design for subsequent re-use with another circuit design. Embodiments enable analog assertion handling while simultaneously depicting a circuit design in a schematic and/or layout editor window. Embodiments capture referenced circuit objects and parameterize the assertion for numerical values and connectivity. A designer may publish the assertion and annotate it with descriptive metadata, possibly with other assertions of related functionality, to a library accessible by users of analog design and verification tools. Another designer may re-use the assertion by searching for and selecting a relevant published assertion, instantiating and binding the selected assertion to specific elements of a second circuit design, and verify the assertion for the second circuit design.

Abstract translation: 一种用于管理模拟断言发布和重用于模拟和混合信号电路设计的系统和方法。 基于图形用户界面的环境允许电路设计人员为电路设计创建，验证，形式化和发布模拟断言，以便随后再次使用电路设计。 实施例使模拟断言处理同时在原理图和/或布局编辑器窗口中描绘电路设计。 实施例捕获参考的电路对象并参数化数值和连通性的断言。 设计人员可以通过模拟设计和验证工具的用户访问的库来发布断言并将其描述性元数据（可能与其他相关功能的断言）注释在一起。 另一设计者可以通过搜索和选择相关的已公布的断言来重新使用断言，将所选择的断言实例化并将其绑定到第二电路设计的特定元件，并验证第二电路设计的断言。

公开(公告)号：US09589085B1

公开(公告)日：2017-03-07

申请号：US14559420

申请日：2014-12-03

Applicant: Cadence Design Systems, Inc.

Inventor： Donald J. O'Riordan ,  Keith Dennison ,  Vuk Borich

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F2217/04

Abstract: A system, method, and computer program product for viewing analog simulation check violations in an EDA framework. Embodiments combine input data tables into a single data table for each check type using SQL inner join operations, create a SQL view of the single data table to list individual check violations, and output the view for user inspection of the corresponding check violations. Embodiments normalize the input data tables to include details of circuit nodes, elements, and paths implicated in the check violations. Additional views combine views of different check types into unified summary tables. Embodiments create a second view to aggregate individual check violations that involve the same circuit objects over time, and output the second view. Output views are self-describing, to enable a single graphical user interface to operate across multiple simulator versions. Metadata tables describe data types presented in various view columns, and user interactions allowed therewith.

Abstract translation: 用于在EDA框架中查看模拟模拟检查违规的系统，方法和计算机程序产品。 实施例将输入数据表组合到每个检查类型的单个数据表中，使用SQL内部连接操作，创建单个数据表的SQL视图以列出单独的检查违规，并输出用于检查相应检查违规的视图。 实施例将输入数据表格化为包括涉及检查违规的电路节点，元件和路径的细节。 其他视图将不同检查类型的视图合并为统一汇总表。 实施例创建第二视图以汇总随着时间推移涉及相同电路对象的单独检查违规，并输出第二视图。 输出视图是自我描述的，以使单个图形用户界面能够跨多个模拟器版本运行。 元数据表描述了各种视图列中提供的数据类型，并允许用户交互。

公开(公告)号：US09779188B1

公开(公告)日：2017-10-03

申请号：US14476456

申请日：2014-09-03

Applicant: Cadence Design Systems, Inc.

Inventor： Yue Li ,  Vuk Borich

IPC: G06F17/50 ,  G06F17/30

CPC classification number: G06F17/5009 ,  G06F17/30286

Abstract: Aspects of the present invention provide a system and method to estimate the amount of memory a harmonic balance analysis will require by measuring the memory allocated for a circuit database for a circuit undergoing harmonic balance analysis, determining the problem size of the harmonic balance analysis based on the information in the database, calculating the amount of memory for matrices, solution and auxiliary vectors needed for the harmonic balance analysis, and estimating the additional memory needed to complete a Newton iteration of the harmonic balance analysis using previously compiled statistical distributions. The total needed memory will be the sum of the measured, calculated, and estimated needed memory. A lower and an upper bound estimation of the total memory usage is provided. This information can be used by the circuit or system designer and/or an analysis or simulation tool for planning the computing resources necessary to execute the harmonic balance analysis.

公开(公告)号：US10084476B1

公开(公告)日：2018-09-25

申请号：US15847604

申请日：2017-12-19

Applicant: Cadence Design Systems, Inc.

Inventor： Jianzhou Zhao ,  Daniel de Fonseca Munford Argollo ,  Vuk Borich ,  Hongzhou Liu

IPC: H03M7/30

CPC classification number: H03M7/30 ,  H03M7/3084

Abstract: A method including separating multiple signal waveforms into multiple blocks forming a sequence is provided. Each of the blocks includes at least a portion of each of the multiple signal waveforms. The method includes identifying a shared time portion and a shared signal portion for the signal waveforms within a first block from the multiple blocks and selecting a format for the first block based on a block size of the first block and a block read time of the first block. The method also includes compressing data in the first block based on the shared time portion, the shared signal portion, a preceding block and a subsequent block in the sequence, and storing the first block in a memory based on the format selected for the first block.