公开(公告)号：US10402530B1

公开(公告)日：2019-09-03

申请号：US15396156

申请日：2016-12-30

Applicant: Cadence Design Systems, Inc.

Inventor： Karun Sharma ,  Yu Liu ,  Subhashis Mandal ,  Kanaka Raju Gorle ,  Jeff Taraldson

IPC: G06F17/50

Abstract: Disclosed are techniques for implementing placement using row templates for an electronic design using row templates. These techniques identify or create a row region in a layout of an electronic design. A row template is applied to the row region to create one or more placement rows in the row region. One or more layout circuit components may then be placed into one or more rows or at one or more locations to create a legal placement layout by guiding placement of the one or more layout circuit components with the row template.

公开(公告)号：US11790147B1

公开(公告)日：2023-10-17

申请号：US17532087

申请日：2021-11-22

Applicant: Cadence Design Systems, Inc.

Inventor： Hongzhou Liu ,  Rahaprian Premavathi Mudiarasan ,  Sandipan Ghosh ,  Hui Xu ,  Chris (Shyh-Chang) Lin ,  Joshua Baudhuin ,  Ron Pyke ,  Juno Lin ,  Allen You ,  Yu Liu ,  Jiulong Zhang ,  Thomas Richards

IPC: G06F30/3953 ,  G06F30/31 ,  G06F30/398 ,  G06F30/3947 ,  G06F30/394

CPC classification number: G06F30/3953 ,  G06F30/31 ,  G06F30/394 ,  G06F30/398 ,  G06F30/3947

Abstract: Embodiments include herein are directed towards a method for electronic circuit design. Embodiments may include receiving, using a processor, an electronic design library including a plurality of design rules. Embodiments may include generating a routing graph, based upon, at least in part, the plurality of design rules, wherein the routing graph is a virtual representation of all of the available routing space for all routing layers associated with an electronic design. Embodiments may further include dynamically updating the routing graph at a graphical user interface, based upon, at least in part, a creation of a routing segment or a via at the graphical user interface.