公开(公告)号：US20130325156A1

公开(公告)日：2013-12-05

申请号：US13485862

申请日：2012-05-31

申请人： Casey J. Grant ,  Kurt A. Tallman ,  Sebastian T. Ventrone

发明人： Casey J. Grant ,  Kurt A. Tallman ,  Sebastian T. Ventrone

IPC分类号： G05B13/02

CPC分类号： G05B19/4097 ,  G05B2219/32031 ,  G05B2219/32033 ,  G05B2219/45031

摘要： Disclosed are embodiments of an improved design method, the results of which are a final design structure for an integrated circuit that incorporates, not only layout information, but also client-specific manufacturing information (e.g., import/export information, service requests, processing directives, purchase order requirements, design rule information, etc.) in the same data format in hierarchical form. Also disclosed are embodiments of a manufacturing control method and system. In these embodiments, a final design structure, such as that described above, is received at tape-in. The information contained therein (particularly, the client-specific manufacturing information) is sorted by type and then forwarded to the appropriate tools within the manufacturing facility for processing. By providing the client-specific manufacturing information directly to each manufacturing facility in the final design structure in conjunction with the layout information, the embodiments eliminate the need for independent information gathering by each manufacturing facility.

摘要翻译： 公开了一种改进的设计方法的实施例，其结果是集成电路的最终设计结构，不仅包括布局信息，而且包括客户特定制造信息（例如，导入/导出信息，服务请求，处理指令 ，采购订单要求，设计规则信息等）以相同的数据格式分层格式。 还公开了制造控制方法和系统的实施例。 在这些实施例中，诸如上述的最终设计结构在磁带入口处被接收。 其中包含的信息（特别是客户特定的制造信息）按类型排序，然后转发到制造设施内的适当工具进行处理。 结合布局信息，通过在终端设计结构中直接向每个制造设施提供特定于客户的制造信息，实施例消除了对每个制造设备的独立信息收集的需要。

公开(公告)号：US08849440B2

公开(公告)日：2014-09-30

申请号：US13485862

申请日：2012-05-31

申请人： Casey J. Grant ,  Kurt A. Tallman ,  Sabastian T. Ventrone

发明人： Casey J. Grant ,  Kurt A. Tallman ,  Sabastian T. Ventrone

IPC分类号： G05B13/02

CPC分类号： G05B19/4097 ,  G05B2219/32031 ,  G05B2219/32033 ,  G05B2219/45031

摘要： Disclosed are embodiments of an improved design method, the results of which are a final design structure for an integrated circuit that incorporates, not only layout information, but also client-specific manufacturing information (e.g., import/export information, service requests, processing directives, purchase order requirements, design rule information, etc.) in the same data format in hierarchical form. Also disclosed are embodiments of a manufacturing control method and system. In these embodiments, a final design structure, such as that described above, is received at tape-in. The information contained therein (particularly, the client-specific manufacturing information) is sorted by type and then forwarded to the appropriate tools within the manufacturing facility for processing. By providing the client-specific manufacturing information directly to each manufacturing facility in the final design structure in conjunction with the layout information, the embodiments eliminate the need for independent information gathering by each manufacturing facility.

摘要翻译： 公开了一种改进的设计方法的实施例，其结果是集成电路的最终设计结构，不仅包括布局信息，而且包括客户特定制造信息（例如，导入/导出信息，服务请求，处理指令 ，采购订单要求，设计规则信息等）以相同的数据格式分层格式。 还公开了制造控制方法和系统的实施例。 在这些实施例中，诸如上述的最终设计结构在磁带入口处被接收。 其中包含的信息（特别是客户特定的制造信息）按类型排序，然后转发到制造设施内的适当工具进行处理。 结合布局信息，通过在终端设计结构中直接向每个制造设施提供特定于客户的制造信息，实施例消除了对每个制造设备的独立信息收集的需要。

公开(公告)号：US06461877B1

公开(公告)日：2002-10-08

申请号：US09608534

申请日：2000-06-30

申请人： Karen L. Holloway ,  Kurt A. Tallman ,  Robert C. Wong

发明人： Karen L. Holloway ,  Kurt A. Tallman ,  Robert C. Wong

IPC分类号： H01L2166

CPC分类号： H01L21/76816 ,  G06F17/5077

摘要： Described herein is a method for selectively enlarging vias connecting two different layers of conductors in a semiconductor device. Whether or not an individual via is extended on each of its edges is determined by the distance of the edge to the neighboring features. Since many vias can be selectively enlarged along one or more edges without infringing upon neighboring structures, via integrity and conductive characteristics are improved.

摘要翻译： 这里描述了一种用于选择性地扩大在半导体器件中连接两个不同导体层的通孔的方法。 单个通孔是否在其每个边缘上延伸是由边缘到相邻特征的距离决定的。 由于可以沿着一个或多个边缘选择性地扩大许多通孔，而不会侵犯相邻的结构，从而提高了完整性和导电特性。

公开(公告)号：US06261945B1

公开(公告)日：2001-07-17

申请号：US09501649

申请日：2000-02-10

申请人： Henry A. Nye, III ,  Vincent J. McGahay ,  Kurt A. Tallman

发明人： Henry A. Nye, III ,  Vincent J. McGahay ,  Kurt A. Tallman

IPC分类号： H01L214763

CPC分类号： H01L23/564 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A copper-interconnect, low-K dielectric integrated circuit has reduced corrosion of the interconnect when the crackstop next to the kerf is also used as the primacy barrier to oxygen diffusion through the dielectric, with corresponding elements of the crackstop being constructed simultaneously with the circuit interconnect elements; e.g. horizontal interconnect elements have a corresponding structure in the crackstop and vias between interconnect layers have corresponding structures in the crackstop.

摘要翻译： 当铜线互连低K电介质集成电路当切口旁边的裂缝也被用作通过电介质的氧扩散的主要障碍时，互连的腐蚀减弱，裂缝的相应元件与电路同时构成 互连元件; 例如 水平互连元件在断裂器中具有相应的结构，并且互连层之间的通孔在裂缝挡板中具有对应的结构。