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公开(公告)号：US07723823B2
公开(公告)日：2010-05-25
申请号：US12178800
申请日：2008-07-24
申请人： Chai Ean Gill , Changsoo Hong , James D. Whitfield , Rouying Zhan
发明人： Chai Ean Gill , Changsoo Hong , James D. Whitfield , Rouying Zhan
IPC分类号： H01L23/62
CPC分类号： H01L27/0259 , H01L29/735 , H01L29/861
摘要： An improved lateral bipolar electrostatic discharge (ESD) protection device (40) comprises a semiconductor (SC) substrate (42), an overlying epitaxial SC layer (44), emitter-collector regions (48, 50) laterally spaced apart by a first distance (52) in the SC layer, a base region (54) adjacent the emitter region (48) extending laterally toward and separated from the collector region (50) by a base-collector spacing (56) that is selected to set the desired trigger voltage Vt1. By providing a buried layer region (49) under the emitter region (48) Ohmically coupled thereto, but not providing a comparable buried layer region (51) under the collector region (50), an asymmetrical structure is obtained in which the DC trigger voltage (Vt1DC) and transient trigger voltage (Vt1TR) are closely matched so that |Vt1TR−Vt1DC|˜0. This close matching increases the design margin and provides a higher performance ESD device (40) that is less sensitive to process variations, thereby improving manufacturing yield and reducing cost.
摘要翻译： 改进的侧向双极性静电放电（ESD）保护装置（40）包括半导体（SC）衬底（42），上覆外延SC层（44），发射极 - 集电区域（48,50），横向间隔开第一距离 （52），邻近所述发射极区域（48）的基极区域（54），所述基极区域（54）通过基极 - 集电极间隔（56）侧向朝向并且与所述集电极区域（50）分离，所述基极集电极间隔（56）被选择以设定所述期望的触发 电压Vt1。 通过在发射极区域（48）的下方设置一个掩埋层区域（49），所述掩埋层区域（49）与其集电极区域（50）的欧姆耦合，但不提供可比较的掩埋层区域（51），获得非对称结构，其中直流触发电压 （Vt1DC）和瞬态触发电压（Vt1TR）紧密匹配，使得| Vt1TR-Vt1DC | ~0。 这种紧密匹配增加了设计裕度，并提供了对工艺变化不那么敏感的更高性能的ESD器件（40），从而提高了制造产量并降低了成本。
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公开(公告)号：US20100019341A1
公开(公告)日：2010-01-28
申请号：US12178800
申请日：2008-07-24
申请人： Chai Ean Gill , Changsoo Hong , James D. Whitfield , Rouying Zhan
发明人： Chai Ean Gill , Changsoo Hong , James D. Whitfield , Rouying Zhan
IPC分类号： H01L23/62
CPC分类号： H01L27/0259 , H01L29/735 , H01L29/861
摘要： An improved lateral bipolar electrostatic discharge (ESD) protection device (40) comprises a semiconductor (SC) substrate (42), an overlying epitaxial SC layer (44), emitter-collector regions (48, 50) laterally spaced apart by a first distance (52) in the SC layer, a base region (54) adjacent the emitter region (48) extending laterally toward and separated from the collector region (50) by a base-collector spacing (56) that is selected to set the desired trigger voltage Vt1. By providing a buried layer region (49) under the emitter region (48) Ohmically coupled thereto, but not providing a comparable buried layer region (51) under the collector region (50), an asymmetrical structure is obtained in which the DC trigger voltage (Vt1DC) and transient trigger voltage (Vt1TR) are closely matched so that ∥Vt1TR−Vt1DC∥˜0. This close matching increases the design margin and provides a higher performance ESD device (40) that is less sensitive to process variations, thereby improving manufacturing yield and reducing cost.
摘要翻译： 改进的侧向双极性静电放电（ESD）保护装置（40）包括半导体（SC）衬底（42），上覆外延SC层（44），发射极 - 集电区域（48,50），横向间隔开第一距离 （52），邻近所述发射极区域（48）的基极区域（54），所述基极区域（54）通过基极 - 集电极间隔（56）侧向朝向并且与所述集电极区域（50）分离，所述基极集电极间隔（56）被选择以设定所述期望的触发 电压Vt1。 通过在发射极区域（48）的下方设置一个掩埋层区域（49），所述掩埋层区域（49）与其集电极区域（50）的欧姆耦合，但不提供可比较的掩埋层区域（51），获得非对称结构，其中直流触发电压 （Vt1DC）和瞬态触发电压（Vt1TR）紧密匹配，使得‖Vt1TR-Vt1DC‖〜0。 这种紧密匹配增加了设计裕度，并提供了对工艺变化不那么敏感的更高性能的ESD器件（40），从而提高了制造产量并降低了成本。
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公开(公告)号：US09786652B2
公开(公告)日：2017-10-10
申请号：US14854366
申请日：2015-09-15
IPC分类号： H01L29/74 , H01L29/747 , H01L29/00 , H01L21/331 , H01L27/082 , H01L29/73 , H01L27/02 , H01L29/66 , H01L23/60 , H01L29/06 , H01L29/08 , H01L29/10
CPC分类号： H01L27/0259 , H01L23/60 , H01L27/0248 , H01L27/0262 , H01L27/082 , H01L29/0649 , H01L29/0808 , H01L29/0821 , H01L29/1008 , H01L29/66234 , H01L29/6625 , H01L29/73 , H01L29/7317 , H01L2924/0002 , H01L2924/00
摘要： An ESD protection device is fabricated in a semiconductor substrate that includes a semiconductor layer having a first conductivity type. A first well implantation procedure implants dopant of a second conductivity type in the semiconductor layer to form inner and outer sinker regions. The inner sinker region is configured to establish a common collector region of first and second bipolar transistor devices. A second well implantation procedure implants dopant of the first conductivity type in the semiconductor layer to form respective base regions of the first and second bipolar transistor devices. Conduction of the first bipolar transistor device is triggered by breakdown between the inner sinker region and the base region of the first bipolar transistor device. Conduction of the second bipolar transistor device is triggered by breakdown between the outer sinker region and the base region of the second bipolar transistor device.
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公开(公告)号：US20140225156A1
公开(公告)日：2014-08-14
申请号：US13764523
申请日：2013-02-11
申请人： Rouying Zhan , Chai Ean Gill , William G. Cowden , Changsoo Hong
发明人： Rouying Zhan , Chai Ean Gill , William G. Cowden , Changsoo Hong
CPC分类号： H01L29/73 , H01L27/0277 , H01L29/0653 , H01L29/66325 , H01L29/735 , H01L29/7835
摘要： An electrostatic discharge (ESD) protection device includes a semiconductor substrate, a base region in the semiconductor substrate and having a first conductivity type, an emitter region in the base region and having a second conductivity type, a collector region in the semiconductor substrate, spaced from the base region, and having the second conductivity type, a breakdown trigger region having the second conductivity type, disposed laterally between the base region and the collector region to define a junction across which breakdown occurs to trigger the ESD protection device to shunt ESD discharge current, and a gate structure supported by the semiconductor substrate over the breakdown trigger region and electrically tied to the base region and the emitter region. The lateral width of the breakdown trigger region is configured to establish a voltage level at which the breakdown occurs.
摘要翻译： 静电放电（ESD）保护装置包括半导体衬底，半导体衬底中的基极区域，具有第一导电类型，基极区域中的发射极区域，具有第二导电类型，半导体衬底中的集电极区域间隔开 具有第二导电类型的具有第二导电类型的击穿触发区域横向设置在基极区域和集电极区域之间以限定发生击穿的结，以触发ESD保护装置以分流ESD放电 电流以及由击穿触发区域上的半导体衬底支撑并电连接到基极区域和发射极区域的栅极结构。 击穿触发区域的横向宽度被配置成建立发生击穿的电压电平。
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公开(公告)号：US09583603B2
公开(公告)日：2017-02-28
申请号：US13764523
申请日：2013-02-11
申请人： Rouying Zhan , Chai Ean Gill , William G. Cowden , Changsoo Hong
发明人： Rouying Zhan , Chai Ean Gill , William G. Cowden , Changsoo Hong
CPC分类号： H01L29/73 , H01L27/0277 , H01L29/0653 , H01L29/66325 , H01L29/735 , H01L29/7835
摘要： An electrostatic discharge (ESD) protection device includes a semiconductor substrate, a base region in the semiconductor substrate and having a first conductivity type, an emitter region in the base region and having a second conductivity type, a collector region in the semiconductor substrate, spaced from the base region, and having the second conductivity type, a breakdown trigger region having the second conductivity type, disposed laterally between the base region and the collector region to define a junction across which breakdown occurs to trigger the ESD protection device to shunt ESD discharge current, and a gate structure supported by the semiconductor substrate over the breakdown trigger region and electrically tied to the base region and the emitter region. The lateral width of the breakdown trigger region is configured to establish a voltage level at which the breakdown occurs.
摘要翻译： 静电放电（ESD）保护装置包括半导体衬底，半导体衬底中的基极区域，具有第一导电类型，基极区域中的发射极区域，具有第二导电类型，半导体衬底中的集电极区域间隔开 具有第二导电类型的具有第二导电类型的击穿触发区域横向设置在基极区域和集电极区域之间以限定发生击穿的结，以触发ESD保护装置以分流ESD放电 电流以及由击穿触发区域上的半导体衬底支撑并电连接到基极区域和发射极区域的栅极结构。 击穿触发区域的横向宽度被配置为建立发生击穿的电压电平。
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公开(公告)号：US09177952B2
公开(公告)日：2015-11-03
申请号：US14053716
申请日：2013-10-15
IPC分类号： H01L29/74 , H01L29/747 , H01L29/00 , H01L21/331 , H01L27/082 , H01L29/73 , H01L27/02 , H01L29/66 , H01L23/60
CPC分类号： H01L27/0259 , H01L23/60 , H01L27/0248 , H01L27/0262 , H01L27/082 , H01L29/0649 , H01L29/0808 , H01L29/0821 , H01L29/1008 , H01L29/66234 , H01L29/6625 , H01L29/73 , H01L29/7317 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) protection device includes a semiconductor substrate comprising a buried insulator layer and a semiconductor layer over the buried insulator layer having a first conductivity type, and first and second bipolar transistor devices disposed in the semiconductor layer, laterally spaced from one another, and sharing a common collector region having a second conductivity type. The first and second bipolar transistor devices are configured in an asymmetrical arrangement in which the second bipolar transistor device includes a buried doped layer having the second conductivity type and extending along the buried insulator layer from the common collector region across a device area of the second bipolar transistor device.
摘要翻译： 静电放电（ESD）保护装置包括半导体衬底，该半导体衬底包括掩埋绝缘体层和在具有第一导电类型的掩埋绝缘体层上的半导体层，以及设置在半导体层中的彼此横向间隔开的第一和第二双极晶体管器件 并且共享具有第二导电类型的公共收集器区域。 第一和第二双极晶体管器件被配置成非对称布置，其中第二双极晶体管器件包括具有第二导电类型的掩埋掺杂层，并且沿着埋在绝缘体层的跨第二极二极管的器件区域的公共集电极区域延伸 晶体管器件。
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公开(公告)号：US20160005730A1
公开(公告)日：2016-01-07
申请号：US14854366
申请日：2015-09-15
CPC分类号： H01L27/0259 , H01L23/60 , H01L27/0248 , H01L27/0262 , H01L27/082 , H01L29/0649 , H01L29/0808 , H01L29/0821 , H01L29/1008 , H01L29/66234 , H01L29/6625 , H01L29/73 , H01L29/7317 , H01L2924/0002 , H01L2924/00
摘要： An ESD protection device is fabricated in a semiconductor substrate that includes a semiconductor layer having a first conductivity type. A first well implantation procedure implants dopant of a second conductivity type in the semiconductor layer to form inner and outer sinker regions. The inner sinker region is configured to establish a common collector region of first and second bipolar transistor devices. A second well implantation procedure implants dopant of the first conductivity type in the semiconductor layer to form respective base regions of the first and second bipolar transistor devices. Conduction of the first bipolar transistor device is triggered by breakdown between the inner sinker region and the base region of the first bipolar transistor device. Conduction of the second bipolar transistor device is triggered by breakdown between the outer sinker region and the base region of the second bipolar transistor device.
摘要翻译： 在包括具有第一导电类型的半导体层的半导体衬底中制造ESD保护器件。 第一阱注入程序在半导体层中注入第二导电类型的掺杂剂以形成内部和外部沉降片区域。 内沉陷区域被配置成建立第一和第二双极晶体管器件的公共集电极区域。 第二阱注入步骤在半导体层中注入第一导电类型的掺杂剂以形成第一和第二双极晶体管器件的相应基极区。 第一双极晶体管器件的导通由第一双极晶体管器件的内部沉降区域和基极区域之间的击穿触发。 第二双极晶体管器件的导通由第二双极晶体管器件的外部沉降区域和基极区域之间的击穿触发。
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公开(公告)号：US20150102384A1
公开(公告)日：2015-04-16
申请号：US14053716
申请日：2013-10-15
CPC分类号： H01L27/0259 , H01L23/60 , H01L27/0248 , H01L27/0262 , H01L27/082 , H01L29/0649 , H01L29/0808 , H01L29/0821 , H01L29/1008 , H01L29/66234 , H01L29/6625 , H01L29/73 , H01L29/7317 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) protection device includes a semiconductor substrate comprising a buried insulator layer and a semiconductor layer over the buried insulator layer having a first conductivity type, and first and second bipolar transistor devices disposed in the semiconductor layer, laterally spaced from one another, and sharing a common collector region having a second conductivity type. The first and second bipolar transistor devices are configured in an asymmetrical arrangement in which the second bipolar transistor device includes a buried doped layer having the second conductivity type and extending along the buried insulator layer from the common collector region across a device area of the second bipolar transistor device.
摘要翻译： 静电放电（ESD）保护装置包括半导体衬底，该半导体衬底包括掩埋绝缘体层和在具有第一导电类型的掩埋绝缘体层上的半导体层，以及设置在半导体层中的彼此横向间隔开的第一和第二双极晶体管器件 并且共享具有第二导电类型的公共收集器区域。 第一和第二双极晶体管器件被配置成非对称布置，其中第二双极晶体管器件包括具有第二导电类型的掩埋掺杂层，并且沿着埋在绝缘体层的跨第二极二极管的器件区域的公共集电极区域延伸 晶体管器件。
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公开(公告)号：US08648419B2
公开(公告)日：2014-02-11
申请号：US12690771
申请日：2010-01-20
申请人： Amaury Gendron , Chai Ean Gill , Changsoo Hong
发明人： Amaury Gendron , Chai Ean Gill , Changsoo Hong
IPC分类号： H01L21/331 , H01L23/62
CPC分类号： H01L29/66234 , H01L27/0259 , H01L29/0821 , H01L29/6625 , H01L29/735
摘要： An electrostatic discharge (ESD) protection clamp (21, 21′, 70, 700) for protecting associated devices or circuits (24), comprises a bipolar transistors (21, 21′, 70, 700) in which doping of facing base (75) and collector (86) regions is arranged so that avalanche breakdown occurs preferentially within a portion (84, 85) of the base region (74, 75) of the device (70, 700) away from the overlying dielectric-semiconductor interface (791). Maximum variations (ΔVt1)MAX of ESD triggering voltage Vt1 as a function of base-collector spacing dimensions D due, for example, to different azimuthal orientations of transistors (21, 21′, 70, 700) on a semiconductor die or wafer is much reduced. Triggering voltage consistency and manufacturing yield are improved.
摘要翻译： 一种用于保护相关器件或电路（24）的静电放电（ESD）保护钳（21,21'，70,700），包括双极晶体管（21,21'，70,700），其中面向基底（75 ）和集电极（86）区域布置成使得雪崩击穿优先地位于远离上覆电介质 - 半导体界面（791）的器件（70,700）的基极区域（74,75）的部分（84,85）内 ）。 作为基极 - 集电极间距尺寸D的函数的ESD触发电压Vt1的最大变化（DeltaVt1）MAX，例如由于半导体晶片或晶片上的晶体管（21,21'，70,700）的不同方位取向是多少 减少 触发电压一致性和制造产量提高。
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公开(公告)号：US09018072B2
公开(公告)日：2015-04-28
申请号：US14168813
申请日：2014-01-30
申请人： Amaury Gendron , Chai Ean Gill , Changsoo Hong
发明人： Amaury Gendron , Chai Ean Gill , Changsoo Hong
IPC分类号： H01L21/331 , H01L29/66 , H01L27/02 , H01L29/735 , H01L29/08
CPC分类号： H01L29/66234 , H01L27/0259 , H01L29/0821 , H01L29/6625 , H01L29/735
摘要： An electrostatic discharge (ESD) protection clamp (21, 21′, 70, 700) for protecting associated devices or circuits (24), comprises a bipolar transistors (21, 21′, 70, 700) in which doping of facing base (75) and collector (86) regions is arranged so that avalanche breakdown occurs preferentially within a portion (84, 85) of the base region (74, 75) of the device (70, 700) away from the overlying dielectric-semiconductor interface (791). Maximum variations (ΔVt1)MAX of ESD triggering voltage Vt1 as a function of base-collector spacing dimensions D due, for example, to different azimuthal orientations of transistors (21, 21′, 70, 700) on a semiconductor die or wafer is much reduced. Triggering voltage consistency and manufacturing yield are improved.
摘要翻译： 一种用于保护相关器件或电路（24）的静电放电（ESD）保护钳（21,21'，70,700），包括双极晶体管（21,21'，70,700），其中面向基底（75 ）和集电极（86）区域布置成使得雪崩击穿优先地位于远离上覆电介质 - 半导体界面（791）的器件（70,700）的基极区域（74,75）的部分（84,85）内 ）。 作为基极 - 集电极间距尺寸D的函数的ESD触发电压Vt1的最大变化（＆Dgr; Vt1）MAX的最大值（例如，由半导体晶粒或晶片上的晶体管（21,21'，70,700）的不同方位取向） 大大减少。 触发电压一致性和制造产量提高。
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