DATA COMPRESSION DEVICES, OPERATING METHODS THEREOF, AND DATA PROCESSING APPARATUSES INCLUDING THE SAME
    1.
    发明申请
    DATA COMPRESSION DEVICES, OPERATING METHODS THEREOF, AND DATA PROCESSING APPARATUSES INCLUDING THE SAME 有权
    数据压缩装置,其操作方法和包括其的数据处理装置

    公开(公告)号:US20120182163A1

    公开(公告)日:2012-07-19

    申请号:US13353984

    申请日:2012-01-19

    IPC分类号: H03M7/30

    CPC分类号: H03M7/30 H03M7/6088

    摘要: A method of operating a data compression device includes analyzing data using an analyzer and generating a result of the analysis, while the data is buffered by an input buffer, and selectively compressing the buffered data according to the result of the analysis. A data compression device includes a data pattern analyzer configured to analyze data transmitted to an input buffer, and generate an analysis code based on the analysis of the data; and a data compression manager configured to selectively compress the data in the input buffer based on the analysis code.

    摘要翻译: 操作数据压缩装置的方法包括使用分析器分析数据并产生分析结果,同时数据由输入缓冲器缓冲,并根据分析结果选择性地压缩缓冲的数据。 数据压缩装置包括数据模式分析器,被配置为分析发送到输入缓冲器的数据,并且基于数据的分析生成分析代码; 以及数据压缩管理器,被配置为基于分析代码选择性地压缩输入缓冲器中的数据。

    Data compression devices, operating methods thereof, and data processing apparatuses including the same
    2.
    发明授权
    Data compression devices, operating methods thereof, and data processing apparatuses including the same 有权
    数据压缩装置及其操作方法以及包括该压缩装置的数据处理装置

    公开(公告)号:US09191027B2

    公开(公告)日:2015-11-17

    申请号:US14173086

    申请日:2014-02-05

    IPC分类号: H03M7/30

    CPC分类号: H03M7/30 H03M7/6088

    摘要: A method of operating a data compression device includes analyzing data using an analyzer and generating a result of the analysis, while the data is buffered by an input buffer, and selectively compressing the buffered data according to the result of the analysis. A data compression device includes a data pattern analyzer configured to analyze data transmitted to an input buffer, and generate an analysis code based on the analysis of the data; and a data compression manager configured to selectively compress the data in the input buffer based on the analysis code.

    摘要翻译: 操作数据压缩装置的方法包括使用分析器分析数据并产生分析结果,同时数据由输入缓冲器缓冲,并根据分析结果选择性地压缩缓冲的数据。 数据压缩装置包括数据模式分析器,被配置为分析发送到输入缓冲器的数据,并且基于数据的分析生成分析代码; 以及数据压缩管理器,被配置为基于分析代码选择性地压缩输入缓冲器中的数据。

    Data compression devices, operating methods thereof, and data processing apparatuses including the same
    3.
    发明授权
    Data compression devices, operating methods thereof, and data processing apparatuses including the same 有权
    数据压缩装置及其操作方法以及包括该压缩装置的数据处理装置

    公开(公告)号:US08659452B2

    公开(公告)日:2014-02-25

    申请号:US13353984

    申请日:2012-01-19

    IPC分类号: H03M7/00

    CPC分类号: H03M7/30 H03M7/6088

    摘要: A method of operating a data compression device includes analyzing data using an analyzer and generating a result of the analysis, while the data is buffered by an input buffer, and selectively compressing the buffered data according to the result of the analysis. A data compression device includes a data pattern analyzer configured to analyze data transmitted to an input buffer, and generate an analysis code based on the analysis of the data; and a data compression manager configured to selectively compress the data in the input buffer based on the analysis code.

    摘要翻译: 操作数据压缩装置的方法包括使用分析器分析数据并产生分析结果,同时数据由输入缓冲器缓冲,并根据分析结果选择性地压缩缓冲的数据。 数据压缩装置包括数据模式分析器,被配置为分析发送到输入缓冲器的数据,并且基于数据的分析生成分析代码; 以及数据压缩管理器,被配置为基于分析代码选择性地压缩输入缓冲器中的数据。

    DECODING DEVICE AND METHOD FOR MIMO SYSTEM
    4.
    发明申请
    DECODING DEVICE AND METHOD FOR MIMO SYSTEM 有权
    用于MIMO系统的解码设备和方法

    公开(公告)号:US20100189200A1

    公开(公告)日:2010-07-29

    申请号:US12602353

    申请日:2008-05-19

    IPC分类号: H04L27/06

    CPC分类号: H04L1/0631 H04L1/006

    摘要: The present invention relates to a decoding device and method for a MIMO system. A linear process is applied to a received signal vector by using a channel matrix estimated from the received signal vector and a poly-diagonalized matrix, and a soft decision value is acquired through a trellis decode by using the linear process result. Since the linear preprocess is performed by using the poly-diagonalized matrix, it is possible to receive a MIMO signal having good packet error rate performance and less complexity. Also, since the tail-biting trellis decoding method is used based on the poly-diagonalized matrix that is generated by poly-diagonalizing the effective channel matrix during the process for eliminating the signal interference, the soft decision value for the symbol can be generated with a simple hardwired device and less operation complexity.

    摘要翻译: 本发明涉及MIMO系统的解码装置和方法。 通过使用从接收信号向量和多对角化矩阵估计的信道矩阵将线性处理应用于接收信号向量,并且通过使用线性处理结果通过网格解码获取软判决值。 由于通过使用多对角化矩阵来执行线性预处理,所以可以接收具有良好的分组错误率性能和较低复杂度的MIMO信号。 另外,由于基于在消除信号干扰的处理期间通过对有效信道矩阵进行多对角化而产生的多对角化矩阵使用尾巴格状解码方法,所以可以生成符号的软判决值, 简单的硬连线设备,操作复杂度较低。

    Memory system with error correction decoder architecture having reduced latency and increased throughput
    5.
    发明授权
    Memory system with error correction decoder architecture having reduced latency and increased throughput 有权
    具有纠错解码器架构的存储器系统具有降低的延迟和增加的吞吐量

    公开(公告)号:US08479085B2

    公开(公告)日:2013-07-02

    申请号:US12191458

    申请日:2008-08-14

    IPC分类号: G06F11/00

    摘要: A memory system includes: a memory controller including an error correction decoder. The error correction decoder includes: a demultiplexer adapted to receive data and demultiplex the data into a first set of data and a second set of data; first and second buffer memories for storing the first and second sets of data, respectively; an error detector; an error corrector; and a multiplexer adapted to multiplex the first set of data and the second set of data and to provide the multiplexed data to the error corrector. While the error corrector corrects errors in the first set of data, the error detector detects errors in the second set of data stored in the second buffer memory.

    摘要翻译: 存储器系统包括:包括纠错解码器的存储器控​​制器。 纠错解码器包括:解复用器,适于接收数据并将数据解复用为第一组数据和第二组数据; 用于分别存储第一和第二组数据的第一和第二缓冲存储器; 误差检测器; 误差校正器 以及多路复用器,其适于多路复用第一组数据和第二组数据,并将复用的数据提供给误差校正器。 当误差校正器校正第一组数据中的错误时,误差检测器检测存储在第二缓冲存储器中的第二组数据中的错误。

    Decoding device and method for MIMO system
    6.
    发明授权
    Decoding device and method for MIMO system 有权
    MIMO系统的解码设备和方法

    公开(公告)号:US08265204B2

    公开(公告)日:2012-09-11

    申请号:US12602353

    申请日:2008-05-19

    IPC分类号: H04L27/06

    CPC分类号: H04L1/0631 H04L1/006

    摘要: The present invention relates to a decoding device and method for a MIMO system. A linear process is applied to a received signal vector by using a channel matrix estimated from the received signal vector and a poly-diagonalized matrix, and a soft decision value is acquired through a trellis decode by using the linear process result. Since the linear preprocess is performed by using the poly-diagonalized matrix, it is possible to receive a MIMO signal having good packet error rate performance and less complexity. Also, since the tail-biting trellis decoding method is used based on the poly-diagonalized matrix that is generated by poly-diagonalizing the effective channel matrix during the process for eliminating the signal interference, the soft decision value for the symbol can be generated with a simple hardwired device and less operation complexity.

    摘要翻译: 本发明涉及MIMO系统的解码装置和方法。 通过使用从接收信号向量和多对角化矩阵估计的信道矩阵将线性处理应用于接收信号向量,并且通过使用线性处理结果通过网格解码获取软判决值。 由于通过使用多对角化矩阵来执行线性预处理,所以可以接收具有良好的分组错误率性能和较低复杂度的MIMO信号。 另外,由于基于在消除信号干扰的处理期间通过对有效信道矩阵进行多对角化而产生的多对角化矩阵使用尾巴格状解码方法,所以可以生成符号的软判决值, 简单的硬连线设备,操作复杂度较低。

    Data storage devices having scale-out devices to map and control groups of non-volatile memory devices

    公开(公告)号:US10452269B2

    公开(公告)日:2019-10-22

    申请号:US15069568

    申请日:2016-03-14

    申请人: Chan Ho Yoon

    发明人: Chan Ho Yoon

    IPC分类号: G06F12/02 G06F3/06 G06F12/10

    摘要: A scale-out device to control a group of non-volatile memory devices from among a plurality of non-volatile memory devices at a data storage device, includes a buffer and a scale-out controller. The buffer is configured to store address mapping information for the group of non-volatile memory devices, the group of non-volatile memory devices being a portion of the plurality of non-volatile memory devices at the data storage device. The scale-out controller is configured to control operation of only the group of non-volatile memory devices according to the address mapping information stored at the buffer.